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Freescale Semiconductor Technical Data
MSC8102 Rev. 12, 4/2005
MSC8102
Quad Core 16-Bit Digital Signal Processor
The raw processing power of this highly integrated systemon-a-chip device enables developers to create nextgeneration networking products that offer tremendous channel densities, while maintaining system flexibility, scalability, and upgradeability. The MSC8102 is offered in two core speed levels: 250 and 275 MHz.
SC140 Extended Core MQBus
SC140 Extended Core 128 SQBus
SC140 Extended Core
SC140 Extended Core
Boot ROM
128 64 IP Master
Local Bus
M2 RAM
32 Timers Memory Controller* UART 4 TDMs IPBus GPIO GIC 32 8 Hardware Semaphores Direct Slave Interface (DSI) Memory Controller* DSI Port 32/64 60x-compatible System Bus 32/64 GPIO Pins Interrupts RS-232
PLL/Clock
PLL
JTAG Port
JTAG
What's New?
Rev. 12 includes the following changes: * New Section 2.5.2 adds startup sequence timing.
64 System Interface DMA
Internal Local Bus Bridge SIU Registers 64
Internal System Bus
*There is a single memory controller that controls access to both the local bus and the system bus.
Figure 1. MSC8102 Block Diagram
The MSC8102 is a highly integrated system-on-a-chip that combines four StarCoreTM SC140 extended cores with an RS-232 serial interface, four time-division multiplexed (TDM) serial interfaces, thirty-two general-purpose timers, a flexible system interface unit (SIU), and a multi-channel DMA engine. The four extended cores can deliver a total 4400 DSP MMACS performance at 275 MHz. Each core has four arithmetic logic units (ALUs), internal memory, a write buffer, and two interrupt controllers. The MSC8102 targets high-bandwidth highly computational DSP applications and is optimized for wireless transcoding and packet telephony as well as highbandwidth base station applications. The MSC8102 delivers enhanced performance while maintaining low power dissipation and greatly reducing system cost.
(c) Freescale Semiconductor, Inc., 2002, 2005. All rights reserved.
Table of Contents
Features............................................................................................................................................................... iv Product Documentation ......................................................................................................................................ix
Chapter 1
Signals/Connections
1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 Power Signals ...................................................................................................................................................1-3 Clock Signals ....................................................................................................................................................1-3 Reset and Configuration Signals.......................................................................................................................1-3 Direct Slave Interface, System Bus, and Interrupt Signals...............................................................................1-4 Memory Controller Signals ............................................................................................................................1-10 GPIO, TDM, UART, and Timer Signals.........................................................................................................1-12 EOnCE Event and JTAG Test Access Port Signals ........................................................................................1-18 Reserved Signals.............................................................................................................................................1-19 Maximum Ratings.............................................................................................................................................2-1 Recommended Operating Conditions...............................................................................................................2-2 Thermal Characteristics ....................................................................................................................................2-2 DC Electrical Characteristics............................................................................................................................2-3 AC Timings.......................................................................................................................................................2-4 FC-CBGA (HCTE) Package Description .........................................................................................................3-1 FC-CBGA (HCTE) Package Mechanical Drawing ........................................................................................3-19 Power Supply Design and Layout Considerations............................................................................................4-1 Connectivity Guidelines ...................................................................................................................................4-3 Recommended Clock Connections for Single-Master Mode with DLL Off....................................................4-4 Power Considerations .......................................................................................................................................4-5 Thermal Design Considerations........................................................................................................................4-6
Chapter 2
Specifications
2.1 2.2 2.3 2.4 2.5
Chapter 3
Packaging
3.1 3.2
Chapter 4
Design Considerations
4.1 4.2 4.3 4.4 4.5
Data Sheet Conventions
OVERBAR
Used to indicate a signal that is active when pulled low (For example, the RESET pin is active when low.) "asserted" Means that a high true (active high) signal is high or that a low true (active low) signal is low "deasserted" Means that a high true (active high) signal is low or that a low true (active low) signal is high Examples: Signal/Symbol Logic State Signal State Voltage PIN True Asserted VIL/VOL PIN False Deasserted VIH/VOH PIN True Asserted VIH/VOH PIN False Deasserted VIL/VOL Note: Values for VIL, VOL, VIH, and VOH are defined by individual product specifications.
MSC8102, Rev. 12 ii Freescale Semiconductor
Program Sequencer SC140 Core JTAG
Address Register File Address ALU EOnCETM
Data ALU Register File Data ALU
Power Management
SC140 Core Xa Xb P 64 64 128
M1 RAM
Instruction Cache QBus 128 PIC IRQs LIC QBus Bank 1 QBus Bank 3
QBC
QBus Interface
IRQs
MQBus SQBus Local Bus
128 128 64
Notes: 1. The arrows show the data transfer direction. 2. The QBus interface includes a bus switch, write buffer, fetch unit, and a control unit that defines four QBus banks. In addition, the QBC handles internal memory contentions.
Figure 2. SC140 Extended Core Block Diagram
MSC8102, Rev. 12 Freescale Semiconductor iii
Features
The tables in this section list the features of the MSC8102 device.
Table 1. Extended SC140 Cores and Core Memories
Feature
Description
Four SC140 cores: * Up to 4400 MMACS using 16 ALUs running at up to 275 MHz. * A total of 1436 KB of internal SRAM (224 KB per core). Each SC140 core provides the following: * Up to 1100 MMACS using an internal 275 MHz clock at 1.6 V. A MAC operation includes a multiplyaccumulate command with the associated data move and pointer update. * 4 ALUs per SC140 core. * 16 data registers, 40 bits each. * 27 address registers, 32 bits each. * Hardware support for fractional and integer data types. * Very rich 16-bit wide orthogonal instruction set. * Up to six instructions executed in a single clock cycle. * Variable-length execution set (VLES) that can be optimized for code density and performance. * IEEE 1149.1 JTAG port. * Enhanced on-device emulation (EOnCE) with real-time debugging capabilities. Each SC140 core is embedded within an extended core that provides the following: * 224 KB M1 memory that is accessed by the SC140 core with zero wait states. * Support for atomic accesses to the M1 memory. * 16 KB instruction cache, 16 ways. * A four-entry write buffer that frees the SC140 core from waiting for a write access to finish. * External cache support by asserting the global signal (GBL) when predefined memory banks are accessed. * Program Interrupt Controller (PIC). * Local Interrupt Controller (LIC). * M2 memory (shared memory):
SC140 Core
Extended Core
Multi-Core Shared Memories M2-Accessible Multi-Core Bus (MQBus)
* * * * *
* A 476 KB memory working at the core frequency. * Accessible from the local bus * Accessible from all four SC140 cores using the MQBus.
* 4 KB bootstrap ROM. A QBus protocol multi-master bus connecting the four SC140 cores to the M2 memory. Data bus access of up to 128-bit read and up to 64-bit write. Operation at the SC140 core frequency. A central efficient round-robin arbiter controlling SC140 core access on the MQBus. Atomic operation control of access to M2 memory by the four SC140 cores and the local bus.
Table 2. Phase-Lock Loop (PLL)
Feature Internal PLL
Description
* Generates up to 275 MHz core clock and up to 91.67 MHz bus clocks for the 60x-compatible local and system buses and other modules. * PLL values are determined at reset based on configuration signal values.
Table 3. Buses and Memory Controller
Feature Dual-Bus Architecture
Description
Can be configured to a 32-bit data system bus and a 64-bit data direct slave interface (DSI) or to a 64-bit data system bus and 32-bit data DSI.
MSC8102, Rev. 12 iv Freescale Semiconductor
Table 3. Buses and Memory Controller (Continued)
Feature
* * * * *
Description
64/32-bit data and 32-bit address 60x bus. Support for multiple-master designs. Four-beat burst transfers (eight-beat in 32-bit wide mode). Port size of 64, 32, 16, and 8 controlled by the internal memory controller. Bus can access external memory expansion or off-device peripherals, or it can enable an external host device to access internal resources. * Slave support, direct access by an external host to internal resources including the M1 and M2 memories. * On-device arbitration between up to four master devices. Provides a 32/64-bit wide slave host interface that operates only as a slave device under the control of an external host processor. * 21 bit address, 32/64-bit data. * Direct access by an external host to on-device resources, including the M1 and the M2 memories. * Synchronous and asynchronous accesses, with burst capability in the synchronous mode. * Dual or Single strobe modes. * Write and Read buffers improves host bandwidth. * Byte enable signals enables 1, 2, 4, and 8 byte write access granularity. * Sliding window mode enables access with reduced number of address pins. * Chip ID decoding enables using one CS signal for multiple DSPs. * Broadcast CS signal enables parallel write to multiple DSPs. * Big-endian, little-endian, and munged little-endian support. Flexible eight-bank memory controller: * Three user-programmable machines (UPMs), general-purpose chip-select machine (GPCM), and a pagemode SDRAM machine * Glueless interface to SRAM, 100 MHz page mode SDRAM, DRAM, EPROM, Flash memory, and other user-definable peripherals. * Byte enables for either 64-bit or 32-bit bus width mode. * Eight external memory banks (banks 0-7). Two additional memory banks (banks 9, 11) control IPBus peripherals and internal memories. Each bank has the following features:
60x-Compatible System Bus
Direct Slave Interface (DSI)
Memory Controller
* * * * * * * * * * * * *
32-bit address decoding with programmable mask. Variable block sizes (32 KB to 4 GB). Selectable memory controller machine. Two types of data errors check/correction: normal odd/even parity and read-modify-write (RMW) odd/even parity for single accesses. Write-protection capability. Control signal generation machine selection on a per-bank basis. Support for internal or external masters on the 60x-compatible system bus. Data buffer controls activated on a per-bank basis. Atomic operation. RMW data parity check (on 60x-compatible system bus only). Extensive external memory-controller/bus-slave support. Parity byte select pin, which enables a fast, glue less connection to RMW-parity devices (on 60x-compatible system bus only). Data pipeline to reduce data set-up time for synchronous devices.
MSC8102, Rev. 12 Freescale Semiconductor v
Table 4. DMA Controller
Feature
* * * *
Description
16 time-multiplexed unidirectional channels. Services up to four external peripherals. Supports DONE or DRACK protocol on two external peripherals. Each channel group services 16 internal requests generated by eight internal FIFOs. Each FIFO generates:
Multi-Channel DMA Controller
* a watermark request to indicate that the FIFO contains data for the DMA to empty and write to the destination * a hungry request to indicate that the FIFO can accept more data.
* Priority-based time-multiplexing between channels using 16 internal priority levels * A flexible channel configuration:
* All channels support all features. * All channels connect to the 60x-compatible system bus or local bus.
* Flyby transfers in which a single data access is transferred directly from the source to the destination without using a DMA FIFO.
Table 5. Serial Interfaces
Feature
Description
Up to four independent TDM modules, each with the following features: * Either totally independent receive and transmit, each having one data line, one clock line, and one frame sync line or four data lines, one clock and one frame sync that are shared between the transmit and receive. * Glueless interface to E1/T1 framers and MVIP, SCAS, and H.110 buses. * Hardware A-law/-law conversion * Up to 50 Mbps per TDM (50 MHz bit clock if one data line is used, 25 MHz if two data lines are used, 12.5 MHz if four data lines are used). * Up to 256 channels. * Up to 16 MB per channel buffer (granularity 8 bytes), where A/ law buffer size is double (granularity 16 byte) * Receive buffers share one global write offset pointer that is written to the same offset relative to their start address. * Transmit buffers share one global read offset pointer that is read from the same offset relative to their start address. * All channels share the same word size. * Two programmable receive and two programmable transmit threshold levels with interrupt generation that can be used, for example, to implement double buffering. * Each channel can be programmed to be active or inactive. * 2-, 4-, 8-, or 16-bit channels are stored in the internal memory as 2-, 4-, 8-, or 16-bit channels, respectively. * The TDM transmitter sync signal (TxTSYN) can be configured as either input or output. * Frame sync and data signals can be programmed to be sampled either on the rising edge or on the falling edge of the clock. * Frame sync can be programmed as active low or active high. * Selectable delay (0-3 bits) between the Frame Sync signal and the beginning of the frame. * MSB or LSB first support.
Time-Division Multiplexing (TDM)
MSC8102, Rev. 12 vi Freescale Semiconductor
Table 5. Serial Interfaces
Feature
Description
* Two signals for transmit data and receive data. * No clock, asynchronous mode. * Can be serviced either by the SC140 DSP cores or an external host on the 60x-compatible system bus or on the DSI. * Full-duplex operation. * Standard mark/space non-return-to-zero (NRZ) format. * 13-bit baud rate selection. * Programmable 8-bit or 9-bit data format. * Separately enabled transmitter and receiver. * Programmable transmitter output polarity. * Two receiver walk-up methods:
* Idle line walk-up. * Address mark walk-up.
UART
* Separate receiver and transmitter interrupt requests. * Eight flags, the first five can generate interrupt request:
* * * * * * * *
* * * * *
Transmitter empty. Transmission complete. Receiver full. Idle receiver input. Receiver overrun. Noise error. Framing error. Parity error.
Receiver framing error detection. Hardware parity checking. 1/16 bit-time noise detection. Maximum bit rate 6.25 Mbps. Single-wire and loop operations.
General-Purpose I/O (GPIO) port
* 32 bidirectional signal lines that either serve the peripherals or act as programmable I/O ports. * Each port can be programmed separately to serve up to two dedicated peripherals, and each port supports open-drain output mode.
Table 6. Miscellaneous Modules
Feature
Description
Two modules of 16 timers each. Each timer has the following features: * Cyclic or one-shot. * Input clock polarity control. * Interrupt request when counting reaches a programmed threshold. * Pulse or level interrupts. * Dynamically updated programmed threshold. * Read counter any time. Watchdog mode for the timers that connect to the device. Eight coded hardware semaphores, locked by simple write access without need for read-modify-write mechanism. * Consolidation of chip maskable interrupt and non-maskable interrupt sources and routing to INT_OUT, NMI_OUT, and to the cores. * Generation of 32 virtual interrupts (eight to each SC140 core) by a simple write access. * Generation of virtual NMI (one to each SC140 core) by a simple write access.
Timers
Hardware Semaphores Global Interrupt Controller (GIC)
MSC8102, Rev. 12 Freescale Semiconductor vii
Table 7. Power and Packaging
Feature Reduced Power Dissipation
* * * *
Description
Low power CMOS design. Separate power supply for internal logic () and I/O (3.3 V). Low-power standby modes. Optimized power management circuitry (instruction-dependent, peripheral-dependent, and modedependent).
Packaging
* 0.8 mm pitch High Temperature Coefficient for Expansion Flip-Chip Ceramic Ball-Grid Array (CBGA (HCTE)). * 431-connection (ball). * 20 mm x 20 mm.
Table 8. Software Support
Feature
Description
The real-time operating system (RTOS) fully supports device architecture (multi-core, memory hierarchy, ICache, timers, DMA, interrupts, peripherals), as follows: * High-performance and deterministic, delivering predictive response time. * Optimized to provide low interrupt latency with high data throughput. * Preemptive and priority-based multitasking. * Fully interrupt/event driven. * Small memory footprint. * Comprehensive set of APIs. * Fully supports DMA controller, interrupts, and timer schemes. * Enables use of one instance of kernel code all four SC140 cores. * Dynamic and static memory allocation from local memory (M1) and shared memory (M2). Enables transparent inter-task communications between tasks running inside the SC140 cores and the other tasks running in on-board devices or remote network devices: * Messaging mechanism between tasks using mailboxes and semaphores. * Networking support; data transfer between tasks running inside and outside the device using networking protocols. * Includes integrated device drivers for such peripherals as TDM, UART, and external buses. * Incorporates task debugging utilities integrated with compilers and vendors. * Board support package (BSP) for the application development system (ADS). * Integrated Development Environment (IDE):
Real-Time Operating System (RTOS)
Multi-Core Support
Distributed System Support
Software Support
* C/C++ compiler with in-line assembly. Enables the developer to generate highly optimized DSP code. It translates code written in C/C++ into parallel fetch sets and maintains high code density. * Librarian. Enables the user to create libraries for modularity. * C libraries. A collection of C/C++ functions for the developer's use. * Linker. Highly efficient linker to produce executables from object code. * Debugger. Seamlessly integrated real-time, non-intrusive multi-mode debugger that enables debugging of highly optimized DSP algorithms. The developer can choose to debug in source code, assembly code, or mixed mode. * Simulator. Device simulation models, enables design and simulation before the hardware arrival. * Profiler. An analysis tool using a patented Binary Code Instrumentation (BCI) technique that enables the developer to identify program design inefficiencies. * Version control. CodeWarrior(R) includes plug-ins for ClearCase, Visual SourceSafe, and CVS.
* * * * External memory. External host. UART. TDM.
Boot Options
MSC8102, Rev. 12 viii Freescale Semiconductor
Table 9. Application Development System (ADS) Board
Feature
* * * *
Description
Host debug through single JTAG connector supports both processors. MSC8101 as the host with both devices on the board. The MSC8101 system bus connects to the DSI. Flash memory for stand-alone applications. Support for the following communications ports:
MSC8102ADS
* * * * * * * *
10/100Base-T. 155 Mbit ATM over Optical. T1/E1 TDM interface. H.110. Voice codec. RS-232. High-density (MICTOR) logic analyzer connectors to monitor signals 6U CompactPCI form factor.
* Emulates DSP farm by connecting to three other ADS boards.
Product Documentation
The documents listed in Table 10 are required for a complete description of the MSC8102 and are necessary to design properly with the part. Obtain documentation from a local Freescale distributor, Freescale Semiconductor sales office, or a Freescale Literature Distribution Center. For documentation updates, visit the Freescale DSP website shown on the last page of this document.
Table 10. MSC8102 Documentation
Name
MSC8102 Technical Data MSC8102 User's Guide MSC8102 Reference Manual StarCoreTM SC140 DSP Core Reference Manual Application Notes
Description
MSC8102 features list and physical, electrical, timing, and package specifications User information include system functionality, getting started tutorial, and programming topics Detailed functional description of the MSC8102 memory and peripheral configuration, operation, and register programming Detailed description of the SC140 family processor core and instruction set Documents describing specific applications or optimized device operation including code examples
Order Number
MSC8102 MSC8102UG MSC8102RM MNSC140CORE See the MSC8102 product website
MSC8102, Rev. 12 Freescale Semiconductor ix
MSC8102, Rev. 12 x Freescale Semiconductor
Signals/Connections
The MSC8102 external signals are organized into functional groups, as shown in Table 1-1 and Figure 1-1.
1
Table 1-1 lists the functional groups, the number of signal connections in each group, and references the table that gives a detailed listing of multiplexed signals within each group. Figure 1-1 shows MSC8102 external signals organized by function.
Table 1-1.
Functional Group
Power (VDD, VCC , and GND) Clock Reset and Configuration DSI, System Bus, and Interrupts Memory Controller General-Purpose Input/Output (GPIO), Time-Division Multiplexed (TDM) Interface, Universal Asynchronous Receiver/ Transmitter (UART), and Timers EOnce and JTAG Test Access Port Reserved (denotes connections that are always reserved)
MSC8102 Functional Signal Groupings Number of Signal Connections
158 3 4 210 16 32
Detailed Description
Table 1-2 on page 1-3 Table 1-3 on page 1-3 Table 1-4 on page 1-3 Table 1-5 on page 1-4 Table 1-6 on page 1-10 Table 1-7 on page 1-12
7 1
Table 1-8 on page 1-18 Table 1-9 on page 1-19
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-1
Signals/Connections
Rev. 1 2
HD0/SWTE HD1/DSISYNC HD2/DSI64 HD3/MODCK1 HD4/MODCK2 HD5/CNFGS HD[6-31] HD[32-63]/D[32-63] HCID[0-3] HA[11-29] HWBS[0-3]/HDBS[0-3]/HWBE[0-3]/HDBE[0-3] HWBS[4-7]/HDBS[4-7]/HWBE[4-7]/HDBE[4-7]/ PWE[4-7]/PSDDQM[4-7]/PBS[4-7] HRDS/HRW/HRDE HBRST HDST0 HDST1 HCS HBCS HTA HCLKIN GPIO0/CHIP_ID0/IRQ4 GPIO1/TIMER0/CHIP_ID1/IRQ5 GPIO2/TIMER1/CHIP_ID2/IRQ6 GPIO3/TDM3TSYN/IRQ1 GPIO4/TDM3TCLK/IRQ2 GPIO5/TDM3TDAT/IRQ3 GPIO6/TDM3RSYN/IRQ4 GPIO7/TDM3RCLK/IRQ5 GPIO8/TDM3RDAT/IRQ6 GPIO9/TDM2TSYN/IRQ7 GPIO10/TDM2TCLK/IRQ8 GPIO11/TDM2TDAT/IRQ9 GPIO12/TDM2RSYN/IRQ10 GPIO13/TDM2RCLK/IRQ11 GPIO14/TDM2RDAT/IRQ12 GPIO15/TDM1TSYN/DREQ1 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO17/TDM1TDAT/DACK1 GPIO18/TDM1RSYN/DREQ2 GPIO19/TDM1RCLK/DACK2 GPIO20/TDM1RDAT GPIO21/TDM0TSYN GPIO22/TDM0TCLK/DONE2/DRACK2 GPIO23/TDM0TDAT/IRQ13 GPIO24/TDM0RSYN/IRQ14 GPIO25/TDM0RCLK/IRQ15 GPIO26/TDM0RDAT GPIO27/URXD/DREQ1 GPIO28/UTXD/DREQ2 GPIO29/CHIP_ID3 GPIO30/TIMER2/TMCLK GPIO31/TIMER3 TMS TDI TCK TRST TDO

1 1 DSI 1 1 BUS 1 1 & SYS 26 32 BUS 4 19 4 4 M E M 1 C 1 1 1 D 1 S 1 I 1 1 1 GPIO 1 GPIO/ 1 TIMER 1 1 1 1 1 1 1 G P 1 I 1 O 1 1 / 1 1 T 1 D 1 M 1 1 1 1 1 1 1 1 1 1 GPIO/ 1 UART 1 GPIO 1 GPIO/ 1 TIMER 1 J T 1 A 1 G 1 1
32 1 1 3 5 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 32 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 3 1 4 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1

A[0-31] TT0 TT1 TT[2-4]/CS[5-7] CS[0-4] TSZ[0-3] TBST IRQ1/GBL IRQ3/BADDR31 IRQ2/BADDR30 IRQ5/BADDR29 BADDR28 BADDR27 BR BG DBG ABB/IRQ4 DBB/IRQ5 TS AACK ARTRY D[0-31] NC/DP0/DREQ1/EXT_BR2 IRQ1/DP1/DACK1/EXT_BG2 IRQ2/DP2/DACK2/EXT_DBG2 IRQ3/DP3/DREQ2/EXT_BR3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ5/DP5/DACK4/EXT_BG3 IRQ6/DP6/DREQ3 IRQ7/DP7/DREQ4 TA TEA NMI NMI_OUT PSDVAL IRQ7/INT_OUT BCTL0 BCTL1/CS[5] BM[0-2]/TC[0-2]/BNKSEL[0-2] ALE PWE[0-3]/PSDDQM[0-3]/PBS[0-3] PSDA10/PGPL0 PSDWE/PGPL1 POE/PSDRAS/PGPL2 PSDCAS/PGPL3 PGTA/PUPMWAIT/PGPL4/PPBS PSDAMUX/PGPL5 TEST EE0 EE1 CLKOUT DLLIN CLKIN PORESET HRESET SRESET RSTCONF
S Y S T E M B U S
M E M C S Y S
T S T C L K R E S E T
Power signals include: VDD , V DDH, VCCSYN, GND, and GNDSYN.
Figure 1-1.
MSC8102 External Signals
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-2 Freescale Semiconductor
1.1 Power Signals
Table 1-2.
Signal Name
VDD
Power Signals
Power and Ground Signal Inputs
Description
Internal Logic Power VDD dedicated for use with the device core. The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VDD power rail. Input/Output Power This source supplies power for the I/O buffers. The user must provide adequate external decoupling capacitors. System PLL Power VCC dedicated for use with the system Phase Lock Loop (PLL). The voltage should be well-regulated and the input should be provided with an extremely low impedance path to the VCC power rail. System Ground An isolated ground for the internal processing logic and I/O buffers. This connection must be tied externally to all chip ground connections, except GNDSYN. The user must provide adequate external decoupling capacitors. System PLL Ground Ground dedicated for system PLL use. The connection should have an extremely low-impedance path to ground.
VDDH VCCSYN
GND
GNDSYN
1.2 Clock Signals
Table 1-3.
Signal Name
CLKIN CLKOUT DLLIN
Clock Signals
Signal Description
Type
Input Output Input Clock In Primary clock input to the MSC8102 PLL. Clock Out The bus clock.
DLLIN Synchronizes the internal clocks with an external device. Note: When the DLL is disabled, pull this pin low (GND).
1.3 Reset and Configuration Signals
Table 1-4.
Signal Name
PORESET RSTCONF
Reset and Configuration Signals
Signal Description
Type
Input Input
Power-On Reset When asserted, this line causes the MSC8102 to enter power-on reset state. Reset Configuration1 Used during reset configuration sequence of the chip. A detailed explanation of its function is provided in the MSC8102 Reference Manual. This signal is sampled upon deassertion of PORESET. Hard Reset When asserted as an input, this signal causes the MSC8102 to enter the hard reset state. When the device is in a hard reset state, it drives the signal as an open-drain output. Soft Reset When asserted as an input, this signal causes the MSC8102 to enter the soft reset state. When the device is in a soft reset state, it drives the signal as an open-drain output.
HRESET
Input/ Output Input/ Output
SRESET
Note:
When PORESET is deasserted, the MSC8102 also samples the following signals: * BM[0-2]--Selects the boot mode. * MODCK[1-2]--Selects the clock configuration. * SWTE--Enables the software watchdog timer. * DSISYNC, DSI64, CNFGS, and CHIP_ID[0-3]--Configures the DSI. Refer to Table 1-5 for details on these signals.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-3
Signals/Connections
1.4 Direct Slave Interface, System Bus, and Interrupt Signals
The direct slave interface (DSI) is combined with the system bus because they share some common signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-5 describes the signals in this group. Note: Although there are fifteen interrupt request (IRQ) connections to the core processors, there are multiple external lines that can connect to these internal signal lines. After reset, the default configuration enables only IRQ[1-7], but includes two input lines each for IRQ[1-3] and IRQ7. The designer must select one line for each required interrupt and reconfigure the other external signal line or lines for alternate functions. Additional alternate IRQ lines and IRQ[8-15] are enabled through the GPIO signal lines.
Table 1-5.
Signal Name
HD0
DSI, System Bus, and Interrupt Signals
Description
Type
Input/ Output Host Data Bus 0 Bit 0 of the DSI data bus. Input
SWTE HD1
Software Watchdog Timer Disable. It is sampled on the rising edge of PORESET signal.
Input/ Output Host Data Bus 1 Bit 1 of the DSI data bus. Input DSI Synchronous Distinguishes between synchronous and asynchronous operation of the DSI. It is sampled on the rising edge of PORESET signal.
DSISYNC
HD2
Input/ Output Host Data Bus 2 Bit 2 of the DSI data bus. Input DSI 64 Defines the width of the DSI and SYSTEM Data buses. It is sampled on the rising edge of PORESET signal.
DSI64 HD3
Input/ Output Host Data Bus 3 Bit 3 of the DSI data bus. Input Clock Mode 1 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
MODCK1 HD4
Input/ Output Host Data Bus 4 Bit 4 of the DSI data bus. Input Clock Mode 2 Defines the clock frequencies. It is sampled on the rising edge of PORESET signal.
MODCK2 HD5
Input/ Output Host Data Bus 5 Bit 5 of the DSI data bus. Input Configuration Source One signal out of two that indicates reset configuration mode. It is sampled on the rising edge of PORESET signal.
CNFGS
HD[6-31] HD[32-63]
Input/Output Host Data Bus 6-31 Bits 6-31 of the DSI data bus. Input/Output Host Data Bus 32-63 Bits 32-63 of the DSI data bus. Input/Output System Bus Data 32-63 In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus.
D[32-63]
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-4 Freescale Semiconductor
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5.
Signal Name
HCID[0-3]
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Input
Host Chip ID 0-3 Carries the chip ID of the DSI. The DSI is accessed only if HCS is asserted and HCID[0-3] matches the Chip_ID, or if HBCS is asserted. Host Bus Address 11-29 Used by external host to access the internal address space. Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host read or write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host write accesses Host Write Byte Strobes (In Asynchronous dual mode) One bit per byte is used as a strobe for host write accesses. Host Data Byte Strobe (in Asynchronous single mode) One bit per byte is used as a strobe for host read or write accesses Host Write Byte Enable (In Synchronous dual mode) One bit per byte is used to indicate a valid data byte for host write accesses. Host Data Byte Enable (in Synchronous single mode) One bit per byte is used as a strobe enable for host read or write accesses System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. Host Read Data Strobe (In Asynchronous dual mode) Used as a strobe for host read accesses. Host Read/Write Select (in Asynchronous/Synchronous single mode) Host read/write select. Host Read Data Enable (In Synchronous dual mode) Indicates valid data for host read accesses. Host Burst The host asserts this pin to indicate that the current transaction is a burst transaction in synchronous mode only. Host Data structure 0 Defines the data structure of the host access in DSI little-endian mode. Host Data structure 1 Defines the data structure of the host access in DSI little-endian mode. Host Chip Select DSI chip select. The DSI is accessed only if HCS is asserted and HCID[0-3] matches the Chip_ID. Host Broadcast Chip Select DSI chip select for broadcast mode. Enables more than one DSI to share the same host chip-select pin for broadcast write accesses.
HA[11-29] HWBS[0-3]
Input Input
HDBS[0-3]
Input
HWBE[0-3]
Input
HDBE[0-3] HWBS[4-7]
Input Input
HDBS[4-7]
Input
HWBE[4-7]
Input
HDBE[4-7]
Input
PWE[4-7]
Output
PSDDQM[4-7]
Output
PBS[4-7]
Output
HRDS
Input
HRW
Input
HRDE HBRST
Input Input
HDST0 HDST1 HCS HBCS
Input Input Input Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-5
Signals/Connections
Table 1-5.
Signal Name
HTA
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Output
Host Transfer Acknowledge Upon a read access, indicates to the host when the data on the data bus is valid. Upon a write access, indicates to the host that the data on the data bus was written to the DSI write buffer. Host Clock Input Host clock signal for DSI synchronous mode.
HCLKIN A[0-31]
Input
Input/Output Address Bus When the MSC8102 is in external master bus mode, these pins function as the system address bus. The MSC8102 drives the address of its internal bus masters and responds to addresses generated by external bus masters. When the MSC8102 is in internal master bus mode, these pins are used as address lines connected to memory devices and are controlled by the MSC8102 memory controller. Input/Output Bus Transfer Type 0 The bus master drives this pins during the address tenure to specify the type of the transaction. Input/Output Bus Transfer Type 1 The bus master drives this pins during the address tenure to specify the type of the transaction. Some applications use only the TT1 signal, for example, from MSC8102 to MSC8102 or MSC8102 to MSC8101 and vice versa. In these applications, TT1 functions as read/write signal. Input/Output Bus Transfer Type 2-4 The bus master drives these pins during the address tenure to specify the type of the transaction. Output Output Chip Select 5-7 Enables specific memory devices or peripherals connected to the system bus. Chip Select 0-4 Enables specific memory devices or peripherals connected to the system bus.
TT0 TT1
TT[2-4]
CS[5-7] CS[0-4] TSZ[0-3]
Input/Output Transfer Size 0-3 The bus master drives these pins with a value indicating the number of bytes transferred in the current transaction. Input/ Output Bus Transfer Burst The bus master asserts this pin to indicate that the current transaction is a burst transaction (transfers eight words). Input Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Global1 When a master within the MSC8102 initiates a bus transaction, it drives this pin. Assertion of this pin indicates that the transfer is global and should be snooped by caches in the system. Interrupt Request 31 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 311 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Interrupt Request 21 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Burst Address 301 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller.
TBST
IRQ1
GBL
Output
IRQ3
Input
BADDR31
Output
IRQ2
Input
BADDR30
Output
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-6 Freescale Semiconductor
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5.
Signal Name
IRQ5
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Input
1
Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Bus Burst Address 291 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Burst Address 28 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller. Burst Address 27 There are five burst address output pins, which are outputs of the memory controller. These pins connect directly to burstable memory devices without internal address incrementors controlled by the MSC8102 memory controller.
BADDR29
Output
BADDR28
Output
BADDR27
Output
BR
Input/Output Bus Request2 When an external arbiter is used, the MSC8102 asserts this pin as an output to request ownership of the bus. When the MSC8102 controller is used as an internal arbiter, an external master asserts this pin as an input to request bus ownership. Input/ Output Bus Grant 2 When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant bus ownership to the MSC8102. Input/ Output Data Bus Grant2 When the MSC8102 acts as an internal arbiter, it asserts this pin as an output to grant data bus ownership to an external bus master. When an external arbiter is used, it asserts this pin as an input to grant data bus ownership to the MSC8102. Input/Output Address Bus Busy1 The MSC8102 asserts this pin as an output for the duration of the address bus tenure. Following an AACK, which terminates the address bus tenure, the MSC8102 deasserts ABB for a fraction of a bus cycle and then stops driving this pin. The MSC8102 does not assume bus ownership as long as it senses this pin is asserted as an input by an external bus master. Input Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
BG
DBG
ABB
IRQ4
DBB
Input/Output Data Bus Busy1 The MSC8102 asserts this pin as an output for the duration of the data bus tenure. Following a TA, which terminates the data bus tenure, the MSC8102 deasserts DBB for a fraction of a bus cycle and then stops driving this pin. The MSC8102 does not assume data bus ownership as long as it senses that this pin is asserted as an input by an external bus master. Input Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
IRQ5
TS
Input/Output Bus Transfer Start Assertion of this pin signals the beginning of a new address bus tenure. The MSC8102 asserts this signal when one of its internal bus masters begins an address tenure. When the MSC8102 senses that this pin is asserted by an external bus master, it responds to the address bus tenure as required (snoop if enabled, access internal MSC8102 resources, memory controller support). Input/ Output Address Acknowledge A bus slave asserts this signal to indicate that it has identified the address tenure. Assertion of this signal terminates the address tenure. Input/ Output Address Retry Assertion of this signal indicates that the bus master should retry the bus transaction. An external master asserts this signal to enforce data coherency with its caches and to prevent deadlock situations.
AACK
ARTRY
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-7
Signals/Connections
Table 1-5.
Signal Name
D[0-31]
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Input/ Output Data Bus Bits 0-31 In write transactions, the bus master drives the valid data on this bus. In read transactions, the slave drives the valid data on this bus. Input The primary configuration selection (default after reset) is reserved.
Reserved DP0
Input/Output System Bus Data Parity 0 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 0 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 0 and D[0-7]. Input DMA Request 1 Used by an external peripheral to request DMA service. External Bus Request 2 An external master asserts this pin to request bus ownership from the internal arbiter. Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DREQ1
EXT_BR2 IRQ1
Input Input
DP1
Input/Output System Bus Data Parity 1 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 1 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 1 and D[8-15]. Output DMA Acknowledge 1 The DMA drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 22 The MSC8102 asserts this pin to grant bus ownership to an external bus master. Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DACK1
EXT_BG2 IRQ2
Output Input
DP2
Input/Output System Bus Data Parity 2 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 2 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 2 and D[16-23]. Output DMA Acknowledge 2 The DMA drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 22 The MSC8102 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DACK2
EXT_DBG2 IRQ3
Output Input
DP3
Input/Output System Bus Data Parity 3 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 3 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 3 and D[24-31]. Input DMA Request 2 Used by an external peripheral to request DMA service. External Bus Request 32 An external master should assert this pin to request bus ownership from the internal arbiter.
DREQ2
EXT_BR3
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-8 Freescale Semiconductor
Direct Slave Interface, System Bus, and Interrupt Signals
Table 1-5.
Signal Name
IRQ4
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Input
Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DP4
Input/Output System Bus Data Parity 4 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 4 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 4 and D[32-39]. Output DMA Acknowledge 3 The DMA drives this output to acknowledge the DMA transaction on the bus. External Data Bus Grant 32 The MSC8102 asserts this pin to grant data bus ownership to an external bus master. Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DACK3
EXT_DBG3 IRQ5
Output Input
DP5
Input/Output System Bus Data Parity 5 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 5 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 5 and D[40-47]. Output DMA Acknowledge 4 The DMA drives this output to acknowledge the DMA transaction on the bus. External Bus Grant 32 The MSC8102 asserts this pin to grant bus ownership to an external bus. Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DACK4
EXT_BG3 IRQ6
Output Input
DP6
Input/Output System Bus Data Parity 6 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 6 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 6 and D[48-55]. Input Input DMA Request 3 Used by an external peripheral to request DMA service. Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
DREQ3 IRQ7
DP7
Input/Output System Bus Data Parity 7 The agent that drives the data bus also drives the data parity signals. The value driven on the data parity 7 pin should give odd parity (odd number of ones) on the group of signals that includes data parity 7 and D[56-63]. Input DMA Request 4 Used by an external peripheral to request DMA service.
DREQ4 TA
Input/Output Transfer Acknowledge Indicates that a data beat is valid on the data bus. For single-beat transfers, TA assertion indicates the termination of the transfer. For burst transfers, TA is asserted eight times to indicate the transfer of eight data beats, with the last assertion indicating the termination of the burst transfer. Input/Output Transfer Error Acknowledge Assertion indicates a failure of the data tenure transaction.The masters within the MSC8102 monitor the state of this pin. The MSC8102 internal bus monitor can assert this pin if it identifies a bus transfer that does not complete.
TEA
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-9
Signals/Connections
Table 1-5.
Signal Name
NMI
DSI, System Bus, and Interrupt Signals (Continued)
Description
Type
Input
Non-Maskable Interrupt When an external device asserts this line, it generates an non-maskable interrupt in the MSC8102, which is processed internally (default) or is directed to an external host for processing (see NMI_OUT). Non-Maskable Interrupt Output An open-drain pin driven from the MSC8102 internal interrupt controller. Assertion of this output indicates that a non-maskable interrupt is pending in the MSC8102 internal interrupt controller, waiting to be handled by an external host.
NMI_OUT
Output
PSDVAL
Input/Output Port Size Data Valid Indicates that a data beat is valid on the data bus. The difference between the TA pin and the PSDVAL pin is that the TA pin is asserted to indicate data transfer terminations, while the PSDVAL signal is asserted with each data beat movement. When TA is asserted, PSDVAL is always asserted. However, when PSDVAL is asserted, TA is not necessarily asserted. For example, if the DMA initiates a double word (2 x 64 bits) transaction to a memory device with a 32-bit port size, PSDVAL is asserted three times without TA and, finally, both pins are asserted to terminate the transfer. Input Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. Interrupt Output Assertion of this output indicates that an unmasked interrupt is pending in the MSC8102 internal interrupt controller.
IRQ7
INT_OUT
Output
Notes:
1. 2.
See the System Interface Unit (SIU) chapter in the MSC8102 Reference Manual for details on how to configure these pins. When used as the bus control arbiter, the MSC8102 can support up to three external bus masters. Each master uses its own set of Bus Request, Bus Grant, and Data Bus Grant signals (BR/BG/DBG, EXT_BR2/EXT_BG2/EXT_DBG2, and EXT_BR3/EXT_BG3/EXT_DBG3). Each of these signal sets must be configured to indicate whether the external master is or is not a MSC8102 master device. See the Bus Configuration Register (BCR) description in the System Interface Unit (SIU) chapter in the MSC8102 Reference Manual for details on how to configure these pins. The second and third set of pins is defined by EXT_xxx to indicate that they can only be used with external master devices. The first set of pins (BR/BG/DBG) have a dual function. When the MSC8102 is not the bus arbiter, these signals (BR/BG/DBG) are used by the MSC8102 to obtain master control of the bus.
1.5 Memory Controller Signals
Refer to the Memory Controller chapter in the MSC8102 Reference Manual for details on configuring these signals.
Table 1-6.
Signal Name
BCTL0
Memory Controller Signals
Description
Type
Output
System Bus Buffer Control 0 Controls buffers on the data bus. Usually used with BCTL1. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System Bus Buffer Control 1 Controls buffers on the data bus. Usually used with BCTL0. The exact function of this pin is defined by the value of SIUMCR[BCTLC]. System and Local Bus Chip Select 5 Enables specific memory devices or peripherals connected to MSC8102 buses. Boot Mode 0-2 Defines the boot mode of the MSC8102. This signal is sampled on PORESET deassertion. Transfer Code 0-2 The bus master drives these pins during the address tenure to specify the type of the code. Bank Select 0-2 Selects the SDRAM bank when the MSC8102 is in 60x-compatible bus mode.
BCTL1
Output
CS5 BM[0-2]
Output Input
TC[0-2]
Input/Output
BNKSEL[0-2]
Output
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-10 Freescale Semiconductor
Memory Controller Signals
Table 1-6.
Signal Name
ALE PWE[0-3]
Memory Controller Signals (Continued)
Description
Type
Output Output
Address Latch Enable Controls the external address latch used in an external master bus. System Bus Write Enable Outputs of the bus general-purpose chip-select machine (GPCM). These pins select byte lanes for write operations. System Bus SDRAM DQM From the SDRAM control machine. These pins select specific byte lanes of SDRAM devices. System Bus UPM Byte Select From the UPM in the memory controller, these signals select specific byte lanes during memory operations. The timing of these pins is programmed in the UPM. The actual driven value depends on the address and size of the transaction and the port size of the accessed device. System Bus SDRAM A10 From the bus SDRAM controller. The precharge command defines which bank is precharged. When the row address is driven, it is a part of the row address. When column address is driven, it is a part of column address. System Bus UPM General-Purpose Line 0 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM Write Enable From the bus SDRAM controller. Should connect to SDRAM WE input. System Bus UPM General-Purpose Line 1 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus Output Enable From the bus GPCM. Controls the output buffer of memory devices during read operations. System Bus SDRAM RAS From the bus SDRAM controller. Should connect to SDRAM RAS input. System Bus UPM General-Purpose Line 2 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus SDRAM CAS From the bus SDRAM controller. Should connect to SDRAM CAS input. System Bus UPM General-Purpose Line 3 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System GPCM TA Terminates external transactions during GPCM operation. Requires an external pull-up resistor for proper operation. System Bus UPM Wait An external device holds this pin low to force the UPM to wait until the device is ready to continue the operation. System Bus UPM General-Purpose Line 4 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM. System Bus Parity Byte Select In systems that store data parity in a separate chip, this output is used as the byte-select for that chip.
PSDDQM[0-3]
Output
PBS[0-3]
Output
PSDA10
Output
PGPL0
Output
PSDWE
Output
PGPL1
Output
POE
Output
PSDRAS
Output
PGPL2
Output
PSDCAS
Output
PGPL3
Output
PGTA
Input
PUPMWAIT
Input
PGPL4
Output
PPBS
Output
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-11
Signals/Connections
Table 1-6.
Signal Name
PSDAMUX
Memory Controller Signals (Continued)
Description
Type
Output
System Bus SDRAM Address Multiplexer Controls the system bus SDRAM address multiplexer when the MSC8102 is in external master mode. System Bus UPM General-Purpose Line 5 One of six general-purpose output lines from the UPM. The values and timing of this pin are programmed in the UPM.
PGPL5
Output
1.6 GPIO, TDM, UART, and Timer Signals
The general-purpose input/output (GPIO), time-division multiplexed (TDM), universal asynchronous receiver/transmitter (UART), and timer signals are grouped together because they use a common set of signal lines. Individual assignment of a signal to a specific signal line is configured through internal registers. Table 1-7 describes the signals in this group.
Table 1-7.
Signal Name
GPIO0
GPIO, TDM, UART, and Timer Signals
Description
Type
Input/Output
General-Purpose Input Output 0 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Chip ID 0 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 1 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. Timer 0 Each signal is configured as either input to or output from the counter. See the MSC8102 Reference for configuration details. Chip ID 1 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 2 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual. Timer 1 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual. Chip ID 2 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal. General-Purpose Input Output 3 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Transmit Frame Sync Transmit frame sync for TDM 3. Interrupt Request 1 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
CHIP_ID0 GPIO1
Input Input/Output
TIMER0
Input/Output
CHIP_ID1 GPIO2
Input Input/Output
TIMER1
Input/Output
CHIP_ID2 GPIO3
Input Input/Output
TDM3TSYN
Input/Output
IRQ1
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-12 Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7.
Signal Name
GPIO4
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 4 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Transmit Clock Transmit Clock for TDM 3 Interrupt Request 2 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input/Output 5 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Serial Transmitter Data The serial transmit data signal for TDM 3. As an output, it provides the DATA_D signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 3 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 6 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Receive Frame Sync The receive sync signal for TDM 3. As an input, this can be the DATA_B data signal for TDM 3.For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 4 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 7 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Receive Clock The receive clock signal for TDM 3. As an output, this can be the DATA_C data signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 5 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 8 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM3 Serial Receiver Data The receive data signal for TDM 3. As an input, this can be the DATA_A data signal for TDM 3. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 6 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
TDM3TCLK
Input
IRQ2
Input
GPIO5
Input/Output
TDM3TDAT
Input/Output
IRQ3
Input
GPIO6
Input/Output
TDM3RSYN
Input/Output
IRQ4
Input
GPIO7
Input/Output
TDM3RCLK
Input/Output
IRQ5
Input
GPIO8
Input/Output
TDM3RDAT
Input/Output
IRQ6
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-13
Signals/Connections
Table 1-7.
Signal Name
GPIO9
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 9 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM2 Transmit frame Sync Transmit Frame Sync for TDM 2. Interrupt Request 7 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 10 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM 2 Transmit Clock Transmit Clock for TDM 2. Interrupt Request 8 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 11 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM2 Serial Transmitter Data The transmit data signal for TDM 2. As an output, this can be the DATA_D data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 9 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 12 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM2 Receive Frame Sync The receive sync signal for TDM 2. As an input, this can be the DATA_B data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 10 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 13 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM2 Receive Clock The receive clock signal for TDM 2. As an input, this can be the DATA_C data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 11 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
TDM2TSYN
Input/Output
IRQ7
Input
GPIO10
Input/Output
TDM2TCLK
Input
IRQ8
Input
GPIO11
Input/Output
TDM2TDAT
Input/Output
IRQ9
Input
GPIO12
Input/Output
TDM2RSYN
Input/Output
IRQ10
Input
GPIO13
Input/Output
TDM2RCLK
Input/Output
IRQ11
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-14 Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7.
Signal Name
GPIO14
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 14 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM2 Serial Receiver Data The receive data signal for TDM 2. As an input, this can be the DATA_A data signal for TDM 2. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 12 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 15 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Transmit frame Sync Transmit Frame Sync for TDM 1. DMA Request 1 Used by an external peripheral to request DMA service. General-Purpose Input Output 16 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Transmit Clock Transmit Clock for TDM 1. DMA Done 1 Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel closing. See the MSC8102 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction.
TDM2RDAT
Input/Output Input
IRQ12
Input
GPIO15
Input/Output
TDM1TSYN
Input/Output
DREQ1 GPIO16
Input Input/Output
TDM1TCLK
Input
DONE1
Input/Output
DRACK1
Output
DMA Data Request Acknowledge 1 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. General-Purpose Input Output 17 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Serial Transmitter Data The transmit data signal for TDM 1. As an output, this can be the DATA_D data signal for TDM 1.For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Acknowledge 1 The DMA controller drives this output to acknowledge the DMA transaction on the bus. General-Purpose Input Output 18 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Receive Frame Sync The receive sync signal for TDM 1. As an input, this can be the DATA_B data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Request 2 Used by an external peripheral to request DMA service.
GPIO17
Input/Output
TDM1TDAT
Input/Output
DACK1 GPIO18
Output Input/Output
TDM1RSYN
Input/Output
DREQ2
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-15
Signals/Connections
Table 1-7.
Signal Name
GPIO19
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 19 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Receive Clock The receive clock signal for TDM 1. As an input, this can be the DATA_C data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. DMA Acknowledge 2 The DMA controller drives this output to acknowledge the DMA transaction on the bus. General-Purpose Input Output 20 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM1 Serial Receiver Data The receive data signal for TDM 1. As an input, this can be the DATA_A data signal for TDM 1. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. General-Purpose Input Output 21 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM0 Transmit frame Sync Transmit Frame Sync for TDM 0. General-Purpose Input Output 22 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM 0 Transmit Clock Transmit Clock for TDM 0. DMA Done 2 Signifies that the channel must be terminated. If the DMA generates DONE, the channel handling this peripheral is inactive. As an input to the DMA, DONE closes the channel much like a normal channel closing. Note: See the MSC8102 Reference Manual chapters on DMA and GPIO for information on configuring the DRACK or DONE mode and pin direction.
TDM1RCLK
Input/Output
DACK2 GPIO20
Output Input/Output
TDM1RDAT
Input/ Output
GPIO21
Input/Output
TDM0TSYN GPIO22
Input/Output Input/Output
TDM0TCLK
Input
DONE2
Input/Output
DRACK2
Output
DMA Data Request Acknowledge 2 Asserted by the DMA controller to indicate that the DMA controller has sampled the peripheral request. General-Purpose Input Output 23 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM0 Serial Transmitter Data The transmit data signal for TDM 0. As an output, this can be the DATA_D data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 13 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core.
GPIO23
Input/Output
TDM0TDAT
Input/Output
IRQ13
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-16 Freescale Semiconductor
GPIO, TDM, UART, and Timer Signals
Table 1-7.
Signal Name
GPIO24
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 24 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM0 Receive Frame Sync The receive sync signal for TDM 0. As an input, this can be the DATA_B data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 14 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 25 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM0 Receive Clock The receive clock signal for TDM 0. As an input, this can be the DATA_C data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. Interrupt Request 15 One of fifteen external lines that can request a service routine, via the internal interrupt controller, from the SC140 core. General-Purpose Input Output 26 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. TDM0 Serial Receiver Data The receive data signal for TDM 0. As an input, this can be the DATA_A data signal for TDM 0. For configuration details, refer to the MSC8102 Reference Manual chapter describing TDM operation. General-Purpose Input Output 27 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. DMA Request 1 Used by an external peripheral to request DMA service. UART Receive Data General-Purpose Input Output 28 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. DMA Request 2 Used by an external peripheral to request DMA service. UART Transmit Data General-Purpose Input Output 29 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. Chip ID 3 Determines the chip ID of the MSC8102 DSI. It is sampled on the rising edge of PORESET signal.
TDM0RSYN
Input/Output
IRQ14
Input
GPIO25
Input/Output
TDM0RCLK
Input/Output
IRQ15
Input
GPIO26
Input/Output
TDM0RDAT
Input/Output
GPIO27
Input/Output
DREQ1
Input
URXD GPIO28
Input Input/Output
DREQ2
Input
UTXD GPIO29
Output Input/Output
CHIP_ID3
Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-17
Signals/Connections
Table 1-7.
Signal Name
GPIO30
GPIO, TDM, UART, and Timer Signals (Continued)
Description
Type
Input/Output
General-Purpose Input Output 30 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs.For details, refer to the MSC8102 Reference Manual GPIO programming model. Timer 2 Each signal is configured as either input to the counter or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual. External TIMER Clock An external timer can connect directly to the SIU as the SIU Clock. General-Purpose Input Output 31 One of 32 GPIO pins used as GPIO or as one of two dedicated inputs or one of two dedicated outputs. For details, refer to the MSC8102 Reference Manual GPIO programming model. Timer 3 Each signal is configured as either input to or output from the counter. For the configuration of the pin direction, refer to the MSC8102 Reference Manual.
TIMER2
Input/Output
TMCLK GPIO31
Input Input/Output
TIMER3
Input/ Output
1.7 EOnCE Event and JTAG Test Access Port Signals
The MSC8102 uses two sets of debugging signals for the two types of internal debugging modules: EOnCE and the JTAG TAP controller. Each internal SC140 core has an EOnce module, but they are all accessed externally by the same two signals EE0 and EE1. The MSC8102 supports the standard set of Test Access Port (TAP) signals defined by IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture specification and described in Table 1-8.
Table 1-8.
Signal Name
EE0 EE1 TCK TDI TDO
JTAG Test Access Port Signals
Signal Description
Type
Input Output Input Input Output
EOnCE Event Bit 0 Used for putting the internal SC140 cores into Debug mode. EOnCE Event Bit 1 Indicates that at least one on-chip SC140 core is in Debug mode. Test Clock--A test clock signal for synchronizing JTAG test logic. Test Data Input--A test data serial signal for test instructions and data. TDI is sampled on the rising edge of TCK and has an internal pull-up resistor. Test Data Output--A test data serial signal for test instructions and data. TDO can be tri-stated. The signal is actively driven in the shift-IR and shift-DR controller states and changes on the falling edge of TCK. Test Mode Select--Sequences the test controller's state machine, is sampled on the rising edge of TCK, and has an internal pull-up resistor. Test Reset--Asynchronously initializes the test controller, has an internal pull-up resistor, and must be asserted after power up.
TMS TRST
Input Input
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-18 Freescale Semiconductor
Reserved Signals
1.8 Reserved Signals
Table 1-9.
Signal Name
TEST
Reserved Signals
Signal Description
Type
Input
Test Used for manufacturing testing. You must connect this pin to GND.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 1-19
Signals/Connections
MSC8102 Quad Core Digital Signal Processor, Rev. 12 1-20 Freescale Semiconductor
Specifications
This chapter contains details on power considerations, DC/AC electrical characteristics, and AC timing specifications. For additional information, see the MSC8102 User's Guide and MSC8102 Reference Manual.
2
2.1 Maximum Ratings
CAUTION
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, normal precautions should be taken to avoid exceeding maximum voltage ratings. Reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (for example, either GND or VDD).
In calculating timing requirements, adding a maximum value of one specification to a minimum value of another specification does not yield a reasonable sum. A maximum specification is calculated using a worst case variation of process parameter values in one direction. The minimum specification is calculated using the worst case for the same parameters in the opposite direction. Therefore, a "maximum" value for a specification never occurs in the same device with a "minimum" value for another specification; adding a maximum to a minimum represents a condition that can never exist. Table 2-1 describes the maximum electrical ratings for the MSC8102. Table 2-1.
Rating
Core supply voltage PLL supply voltage I/O supply voltage Input voltage Maximum operating temperature Minimum operating temperature Storage temperature range Notes: 1. 2. 3.
Absolute Maximum Ratings
Symbol
VDD VCCSYN VDDH VIN TJ TA TSTG
Value
-0.2 to 2.1 -0.2 to 2.1 -0.2 to 4.0 (GND - 0.2) to 4.0 105 -25 -55 to +150
Unit
V V V V C C C
Functional operating conditions are given in Table 2-2. Absolute maximum ratings are stress ratings only, and functional operation at the maximum is not guaranteed. Stress beyond the listed limits may affect device reliability or cause permanent damage. Section 4.5, , on page 4-6 includes a formula for computing the chip junction temperature (TJ).
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-1
Specifications
2.2 Recommended Operating Conditions
Table 2-2 lists recommended operating conditions. Proper device operation outside of these conditions is not guaranteed.
Table 2-2.
Rating
Core supply voltage PLL supply voltage I/O supply voltage Input voltage Operating temperature range
Recommended Operating Conditions
Symbol
VDD VCCSYN VDDH VIN TJ TA
Value
1.55 to 1.7 1.55 to 1.7 3.135 to 3.465 -0.2 to VDDH+0.2 maximum: 105 minimum: -25
Unit
V V V V C C
2.3 Thermal Characteristics
Table 2-3 describes thermal characteristics of the MSC8102 for the FC-CBGA (HCTE) package.
Table 2-3. Thermal Characteristics for FC-CBGA (HCTE) Package
FC-CBGA (HCTE) 20 Characteristic
Junction-to-ambient1, 2 Junction-to-ambient, four-layer board1, 3 Junction-to-board (bottom) Junction-to-case5 Notes: 1.
4
x
20 mm 5 200 ft/min (1 m/s) airflow
20 11
Symbol
RJA or JA RJA or JA RJB or JB RJC or JC
Natural Convection
27 15 4.4 0.3
100 ft/min (0.5 m/s) airflow
22 12
Unit
C/W C/W C/W C/W
2. 3. 4. 5.
Junction temperature is a function of on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. Per SEMI G38-87 and EIA/JESD51-2 with the single layer (1s) board horizontal. Per JESD51-6 with the board horizontal. Thermal resistance between the die and the printed circuit board per JEDEC JESD 51-8. Board temperature is measured on the top surface of the board near the package. Indicates the average thermal resistance between the die and the case top surface as measured by the cold plate method (MIL SPEC-883 Method 1012.1) with the cold plate temperature used for the case temperature.
Section 4.5 describes these characteristics. The application note entitled MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601) describes the performance of the MSC8102 devices under standard thermal test conditions and when mounted in a component array. It also provides guidelines for evaluating board layouts that use MSC8102 devices.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-2 Freescale Semiconductor
DC Electrical Characteristics
2.4 DC Electrical Characteristics
This section describes the DC electrical characteristics for the MSC8102. The measurements in Table 2-4 assume the following system conditions: * * * * TA = 25 C V DD = 1.55-1.7 VDC V DDH = 3.3 V 5% VDC GND = 0 V DC
Note: The leakage current is measured for nominal VDDH and VDD or both VDDH and VDD must vary in the same direction (for example, both VDDH and VDD vary by +2 percent or both vary by -2 percent).
Table 2-4.
Characteristic
Input high voltage , all inputs except CLKIN Input low voltage1 CLKIN input high voltage CLKIN input low voltage Input leakage current, VIN = VDDH Tri-state (high impedance off state) leakage current, VIN = VDDH Signal low input current, V IL = 0.4 V
2 1
DC Electrical Characteristics
Symbol
VIH VIL VIHC VILC IIN IOZ IL IH VOH VOL IDDW -- -- IDDS -- -- P -- -- 1.35 1.47 -- -- W W 88 95 -- -- mA mA 203 222 -- -- mA mA
Min
2.0 GND 2.4 GND -1.0 -1.0 -1.0 -1.0 2.0 --
Typical
3.0 0 3.0 0 0.09 0.09 0.09 0.09 3.0 0
Max
3.465 0.4 3.465 0.4 1 1 1 1 -- 0.4
Unit
V V V V A A A A V V
Signal high input current, VIH = 2.0 V2 Output high voltage, IOH = -2 mA, except open drain pins Output low voltage, IOL= 3.2 mA Internal supply current: * In Wait mode -- 250 MHz -- 275 MHz * In Stop mode -- 250 MHz -- 275 MHz Typical power consumption3 at: * 250 MHz * 275 MHz Notes: 1. 2. 3.
See Figure 2-1 for undershoot and overshoot voltages. Not tested. Guaranteed by design. The typical power was measured using an EFR code with the device running at room temperature (TA = 25C). No peripherals were enabled and ICache was not enabled. The source code was optimized to utilize all the ALUs and AGUs and all four cores. It was created using CodeWarrior(R) 2.5 by Metrowerks(R). These values are provided as examples only. Power consumption is application dependent and varies widely. To assure proper board design with regard to thermal dissipation and proper operating temperatures, evaluate power consumption for your application and use the design guidelines in Chapter 4 and in MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-3
Specifications
VIH
VDDH + 20% VDDH + 10% VDDH
VIL
GND GND - 0.3 V GND - 0.7 V
Must not exceed 10% of clock period
Figure 2-1.
Overshoot/Undershoot Voltage for VIH and VIL
2.5 AC Timings
The following sections include illustrations and tables of clock diagrams, signals, and parallel I/O outputs and inputs. When designing systems such as DSP farms using the DSI, use a device loading of 4 pF per pin. AC timings are based on a 50 pF load, except where noted otherwise, and a 50 transmission line. For any additional pF, add 0.07 ns for the delay and take the RC delay into consideration.
2.5.1
Output Buffer Impedances
Table 2-5.
Output Buffers
Output Buffer Impedances
Typical Impedance ()
35 35 55
System bus Memory controller Parallel I/O Note:
These are typical values at 65C. The impedance may vary by 25% depending on device process and operating temperature.
2.5.2
Start-Up Timing
Starting the device requires coordination among several input sequences including clocking, reset, and power. Section 2.5.3 describes the clocking characteristics. Section 2.5.4 describes the reset and power-up characteristics. You must use the following guidelines when starting up an MSC8102 device: * * * must be asserted externally for the duration of the power-up sequence. See Table 2-10 for timing. If possible, bring up the VDD and VDDH levels together. For designs with separate power supplies, bring up the VDDH levels and then the VDD levels (see Figure 2-3 and Figure 2-4). CLKIN can start toggling after VDDH reaches its nominal level, but it must toggle before VDD reaches 0.5 V to guarantee correct device operation (see Figure 2-2 and Figure 2-4).
PORESET and TRST
The following figures show acceptable start-up sequence examples. Figure 2-2 shows a sequence in which VDD and VDDH are raised together. Figure 2-3 shows a sequence in which CLKIN starts toggling after VDDH reaches its nominal level and before VDD is applied. Figure 2-4 shows a sequence in which VDD is raised after VDDH and CLKIN begins to toggle shortly before VDD reaches the 0.5 V level.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-4 Freescale Semiconductor
AC Timings
VDDH = Nominal Value VDD = Nominal Value
1
3.3 V
VDDH Nominal Level
Voltage
2.2 V 1.6 V VDD Nominal Level
o.5 V
Time
PORESET/TRST Deasserted CLKIN Starts Toggling PORESET/TRST Asserted VDD/VDDH Applied
Figure 2-2.
Start-Up Sequence with VDD and VDDH Raised Together
VDDH = Nominal VDD = Nominal
1
3.3 V
VDDH Nominal
Voltage
1.6 V 1.06 V
VDD Nominal
Time
PORESET/TRST asserted VDDH applied PORESET/TRST Deasserted VDD applied CLKIN starts toggling
Figure 2-3.
Start-Up Sequence with CLKIN Started After VDDH and Before VDD
VDDH = Nominal VDD = Nominal
1
3.3 V
VDDH Nominal
Voltage
1.6 V 1.06 V o.5 V
VDD Nominal
Time
PORESET/TRST asserted VDDH applied VDD applied PORESET/TRST deasserted CLKIN starts toggling
Figure 2-4.
Start-Up Sequence with VDDH Raised Before VDD with CLKIN Started Before VDD = 0.5 V
MSC8102 Quad Core Digital Signal Processor, Rev. 12
Freescale Semiconductor
2-5
Specifications
2.5.3
Clock and Timing Signals
The following sections include a description of clock signal characteristics. Table 2-6 shows the maximum frequency values for internal (core, reference, bus, and DSI) and external (CLKOUT) clocks. The user must ensure that maximum frequency values are not exceeded.
Table 2-6.
Characteristic
Core frequency Reference frequency (REFCLK) Internal bus frequency (BLCK) DSI clock frequency (HCLKIN) External clock output frequency (CLKOUT) Note: The REFCLK is CLKOUT.
Maximum Frequencies
Maximum in MHz
250/275 83.3/91.7 83.3/91.7 if REFCLK 70 MHz, HCLKIN CLKOUT if REFCLK > 70 MHz, HCLKIN 70 MHz 83.3/91.7
Table 2-7.
Characteristics
CLKIN frequency DLLIN frequency BCLK frequency Reference Clock (REFCLK) frequency Output Clock (CLKOUT) frequency SC140 core clock frequency Note:
Clock Frequencies
250 MHz Device 275 MHz Device Min
33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 165 MHz
Symbol Min
FCLKIN FDLLIN FBCLK FREFCLK FCLKOUT FCORE 33 MHz 33 MHz 33 MHz 33 MHz 33 MHz 165 MHz
Max
75 MHz 75 MHz 75 MHz 83.3 MHz 83.3 MHz 250 MHz
Max
75 MHz 75 MHz 75 MHz 91.7 MHz 91.7 MHz 275 MHz
The rise and fall time of external clocks should be 5 ns maximum.
Table 2-8.
Characteristic
Phase jitter between BCLK and DLLIN CLKIN frequency CLKIN slope DLLIN slope CLKOUT frequency jitter 1 CLKOUT phase jitter (in DLLOFF mode)2 Delay between CLKOUT and DLLIN3 Notes: 1. 2. 3.
System Clock Parameters
Minimum
-- 33 -- -- -- -- --
Maximum
0.5 75 5 2 (0.01 x FCLKOUT) + FCLKIN jitter 2 5
Unit
ns MHz ns ns MHz ns ns
Low CLKIN frequency causes poor PLL performance. Choose a FCLKIN value high enough to keep the frequency after predivider (SPLLMFCLK) higher than 16.5 MHz. Peak-to-peak. Not tested. Guaranteed by design.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-6 Freescale Semiconductor
AC Timings
2.5.4
Reset Timing
The MSC8102 has several inputs to the reset logic: * Power-on reset (PORESET) * External hard reset (HRESET) * External soft reset (SRESET) * Software watchdog reset * Bus monitor reset * Host reset command through JTAG All MSC8102 reset sources are fed into the reset controller, which takes different actions depending on the source of the reset. The reset status register indicates the most recent sources to cause a reset. Table 2-9 describes the reset sources.
Table 2-9.
Name
Power-on reset (PORESET)
Reset Sources
Description
Direction
Input
Initiates the power-on reset flow that resets the MSC8102 and configures various attributes of the MSC8102. On PORESET, the entire MSC8102 device is reset. SPLL and DLL states are reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The clock mode (MODCK bits), reset configuration mode, boot mode, Chip ID, and use of either a DSI 64 bits port or a System Bus 64 bits port are configured only when PORESET is asserted. Initiates the hard reset flow that configures various attributes of the MSC8102. While HRESET is asserted, SRESET is also asserted. HRESET is an open-drain pin. Upon hard reset, HRESET and SRESET are driven, the SC140 extended cores are reset, and system configuration is sampled. The most configurable features are reconfigure. These features are defined in the 32-bit hard reset configuration word described in Hard Reset Configuration Word section of the Reset chapter in the MSC8102 Reference Manual. Initiates the soft reset flow. The MSC8102 detects an external assertion of SRESET only if it occurs while the MSC8102 is not asserting reset. SRESET is an open-drain pin. Upon soft reset, SRESET is driven, the SC140 extended cores are reset, and system configuration is maintained. When the MSC8102 watchdog count reaches zero, a software watchdog reset is signalled. The enabled software watchdog event then generates an internal hard reset sequence. When the MSC8102 bus monitor count reaches zero, a bus monitor hard reset is asserted. The enabled bus monitor event then generates an internal hard reset sequence. When a host reset command is written through the Test Access Port (TAP), the TAP logic asserts the soft reset signal and an internal soft reset sequence is generated.
External Hard reset (HRESET)
Input/ Output
External Soft reset (SRESET) Software watchdog reset Bus monitor reset Host reset command through the TAP
Input/ Output Internal Internal Internal
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-7
Specifications
Table 2-10 summarizes the reset actions that occur as a result of the different reset sources.
Table 2-10. Reset Actions for Each Reset Source
Power-On Reset (PORESET) Reset Action/Reset Source External only Hard Reset (HRESET) External or Internal (Software Watchdog or Bus Monitor)
No No No Yes Yes Yes Yes Yes Yes Yes
Soft Reset (SRESET)
External
JTAG Command: EXTEST, CLAMP, or HIGHZ
No No No No No No Yes Depends on command Yes Yes
Configuration pins sampled (refer to Section 2.5.4.1 for details). SPLL and DLL states reset System reset configuration write through the DSI System reset configuration write though the system bus HRESET driven SIU registers reset IPBus Modules Reset (TDM, UART, timers, DSI, IPBus Master, GIC, HS, and GPIO) SRESET driven SC140 extended cores reset MQBS reset
Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
No No No No No No Yes Yes Yes Yes
2.5.4.1 Power-On Reset (PORESET) Pin
Asserting PORESET initiates the power-on reset flow. PORESET and TRST should be asserted external during power-up. CLKIN may start toggling after VDDH reaches the nominal level, but must start toggling before VDD reaches 0.5 V.
2.5.4.2 Reset Configuration
The MSC8102 has two mechanisms for writing the reset configuration: * Through the direct slave interface (DSI), or * Through the system bus When reset configuration written through the system bus, the MSC8102 uses as a configuration master or as a configuration slave. If a configuration slave is selected, but no special configuration word is written, a default configuration word is applied. Fourteen signal levels are sampled on PORESET deassertion to define the Reset Configuration mode and boot and operating conditions (see Chapter 1 for signal descriptions): * * * * * * * *
RSTCONF CNFGS DSISYNC DSI64 CHIP_ID[0-3] BM[0-2] SWTE MODCK[1-2]
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-8 Freescale Semiconductor
AC Timings
2.5.4.3 Reset Timing Tables
Table 2-11 and Figure 2-5 describe the reset timing for a reset configuration write through the direct slave interface (DSI) or through the system bus.
Table 2-11.
No.
1
Timing for a Reset Configuration Write through the DSI or System Bus
Characteristics Expression
16/CLKIN 484.8 213.3 1024/CLKIN 31.03 13.65 800/(CLKIN/PDF) (pre-division factor) 3073/REFCLK 93.12 40.97 0.0 s s s 48.5 32.0 s s s s
Min
Max
--
Unit
ns
Required external PORESET duration minimum * CLKIN = 33 MHz * CLKIN = 75 MHz Delay from deassertion of external PORESET to deassertion of internal PORESET * CLKIN = 33 MHz * CLKIN = 75 MHz Delay from de-assertion of internal PORESET to SPLL lock * CLKIN = 33 MHz * CLKIN = 75 MHz Delay from SPLL lock to DLL lock. * DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz * DLL disabled * * Delay from SPLL and DLL lock to HRESET de-assertion DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz DLL disabled REFCLK = 33 Mhz REFCLK = 75 Mhz
2
3
4
-- 3585/REFCLK
5
108.64 47.5 512/REFCLK 15.52 6.83 3588/REFCLK 108.73 47.84 515/REFCLK 15.61 6.87
s s s s
*
6
Delay from SPLL and DLL lock to SRESET de-assertion * DLL enabled REFCLK = 33 Mhz REFCLK = 75 Mhz * DLL disabled REFCLK = 33 Mhz REFCLK = 75 Mhz Timings are not tested, but are guaranteed by design.
s s s s
Note:
1
RSTCONF, CNFGS, DSISYNC, DSI64 CHIP_ID[0-3], BM[0-2], SWTE, MODCK[1-2] pins are sampled Host programs Reset Configuration Word SPLL and DLL are locked (no external indication)
PORESET Input
PORESET Internal
1+2
HRESET Output (I/O)
2
MODCK[3-5], DLLDIS bits are ready for SPLL.
3+4
SRESET Output (I/O)
SPLL and DLL Reset configuration write locking period. sequence occurs during this When DLL is disabled, period. reset period is shortened by 3073 bus clocks.
5 6
Figure 2-5.
Timing Diagram for a Reset Configuration Write
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-9
Specifications
2.5.5
System Bus Access Timing
2.5.5.1 Core Data Transfers
Generally, all MSC8102 bus and system output signals are driven from the rising edge of the reference clock (REFCLK). The REFCLK is either the DLLIN signal or, if DLL is disabled, the CLKOUT signal. Memory controller signals, however, trigger on four points within a REFCLK cycle. Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising edge of REFCLK (and T3 at the falling edge), as Figure 2-6 shows. Figure 2-6 is a graphical representation of the internal ticks.
REFCLK T1 T2 T3 T4
Figure 2-6.
Internal Tick Spacing for Memory Controller Signals
The UPM machine and GPCM machine outputs change on the internal tick determined by the memory controller configuration. The AC specifications are relative to the internal tick. SDRAM machine outputs change only on the REFCLK rising edge.
Table 2-12.
No.
10 11a 11b 11c 11d
AC Timing for SIU Inputs
Value2
1 4.5 4.3 5.0 3.7 5.0 2.3 4.9 2.6 7 2.3 6.5 3.1 6.9 5.5 7.6 4.0
Characteristic
Hold time for all signals after the 50% level of the REFCLK rising edge ARTRY/ABB/TS set-up time before the 50% level of the REFCLK rising edge DBG/DBB/BG/BR/TC set-up time before the 50% level of the REFCLK rising edge AACK set-up time before the 50% level of the REFCLK rising edge TA/TEA/PSDVAL set-up time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Data bus set-up time before REFCLK rising edge in Normal mode * Pipeline mode * Non-pipeline mode Data bus set-up time before the 50% level of the REFCLK rising edge in ECC and PARITY modes * Pipeline mode * Non-pipeline mode DP set-up time before the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Address bus set-up time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * No extra cycle mode (SIUBCR[EXDD] = 1) Address attributes: TT/TBST/TSIZ/GBL set-up time before the 50% level of the REFCLK rising edge * Extra cycle mode (SIUBCR[EXDD] = 0) * No extra cycle mode (SIUBCR[EXDD] = 1) PUPMWAIT signal set-up time before the 50% level of the REFCLK rising edge 1. 2.
Units
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
12
13
14
15a
15b
161 Notes:
Synchronous operation. Asynchronous operation may have a higher set-up time. Values are measured from the 50% TTL transition level relative to the 50% level of the REFCLK rising edge.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-10 Freescale Semiconductor
AC Timings
Table 2-13.
No.
30 31
AC Timing for SIU Outputs
Value1 Units 30 pF 50 pF
1.0 7.5 8.0 8.7 5.6 7.3 6.3 6.5 9.0 7.0 9.0 7.4 7.0 7.8 ns ns ns ns ns ns ns ns ns ns ns ns ns ns 1.0 6.0 6.5 7.2 4.1 5.8 4.8 5.0 7.5 5.5 7.5 5.9 5.5 6.3
Characteristic
Min delay from the 50% level of the REFCLK for all signals PSDVAL/TEA/TA max delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Address bus max delay from the 50% level of the REFCLK rising edge * Multi-master mode (SIUBCR[EBM] = 1) * Single-master mode (SIUBCR[EBM] = 0) Address attributes: TT/TC/TBST/TSIZ/GBL max delay from the 50% level of the REFCLK rising edge BADDR max delay from the 50% level of the REFCLK rising edge Data bus max delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode DP max delay from the 50% level of the REFCLK rising edge * Pipeline mode * Non-pipeline mode Memory controller signals/ALE max delay from the 50% level of the REFCLK rising edge DBG/BG/BR/DBB max delay from the 50% level of the REFCLK rising edge AACK/ABB/TS/CS max delay from the 50% level of the REFCLK rising edge 1. 2.
32a
32b 32c 33a
33b
34 35a 35b Notes:
Values are measured from the 50% level of the REFCLK rising edge to the 50% signal level. The maximum bus frequency depends on the mode: * In 60x-compatible mode connected to another MSC8102 device, the frequency is determined by adding the input and output longest timing values, which results in a frequency of 75 MHz for 30 pF output capacitance. * In single-master mode, the frequency depends on the timing of the devices connected to the MSC8102.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-11
Specifications
REFCLK 10 AACK/ARTRY/TA/TEA/DBG/BG/BR PSDVAL/ABB/DBB/TS inputs 11
10 12 Data bus inputs--normal mode 10 Data bus inputs--ECC and parity modes DP inputs Address bus/TT[0-4]/TC[0-2]/TBST/TSZ[0-3]/GBL inputs PUPMWAIT input 13 14 15 16 10
30 Minimum delay for all output pins 31 PSDVAL/TEA/TA outputs 32a/b Address bus/TT[0-4]/TC[0-2]/TBST/TSZ[0-3]/GBL outputs BADDR outputs 32c 33a
Data bus outputs DP outputs
33b
Memory controller/ALE outputs
34
35 AACK/ABB/TS/DBG/BG/BR/DBB/CS outputs
Figure 2-7.
Bus Signal Timing
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-12 Freescale Semiconductor
AC Timings
2.5.5.2 DMA Data Transfers
Table 2-14 describes the DMA signal timing.
Table 2-14.
No.
37 38 39 40 41
DMA Signals
Minimum
6 0.5 7 0.5 0.5
Characteristic
DREQ set-up time before the 50% level of the falling edge of REFCLK DREQ hold time after the 50% level of the falling edge of REFCLK DONE set-up time before the 50% level of the rising edge of REFCLK DONE hold time after the 50% level of the rising edge of REFCLK DACK/DRACK/DONE delay after the 50% level of the REFCLK rising edge
Maximum
-- -- -- -- 9
Units
ns ns ns ns ns
signal is synchronized with REFCLK. To achieve fast response, a synchronized peripheral should assert DREQ according to the timings in Table 2-14. Figure 2-8 shows synchronous peripheral interaction.
The DREQ
REFCLK 38 37 DREQ 40 39 DONE 41 DACK/DONE/DRACK
Figure 2-8.
DMA Signals
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-13
Specifications
2.5.6
DSI Timing
The timings in the following sections are based on a 30 pF capacitive load. See Section 2.5.1, Output Buffer Impedances, on page 2-4 for details.
2.5.6.1 DSI Asynchronous Mode
Table 2-15.
No.
100 101 102
DSI Asynchronous Mode Timing
Min
2.3 2.0
Characteristics
Attributes1 set-up time before strobe (HWBS[n]) assertion Attributes hold time after data strobe deassertion Read/Write data strobe deassertion width * DCR[HTAAD] = 1 -- Consecutive access to the same DSI -- Different device with DCR[HTADT] = 01 -- Different device with DCR[HTADT] = 10 -- Different device with DCR[HTADT] = 11 * DCR[HTAAD] = 0 Read data strobe deassertion to output data high impedance Read data strobe assertion to output data active from high impedance Output data hold time after read data strobe deassertion Read/Write data strobe assertion to HTA active from high impedance Output data valid to HTA assertion Read/Write data strobe assertion to HTA valid2 Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 0, HTA at end of access released at logic 0) Read/Write data strobe deassertion to output HTA deassertion. (DCR[HTAAD] = 1, HTA at end of access released at logic 1) Read/Write data strobe deassertion to output HTA high impedance. (DCR[HTAAD] = 1, HTA at end of access released at logic 1 * DCR[HTADT] = 01 * DCR[HTADT] = 10 * DCR[HTADT] = 11 Read/Write data strobe assertion width Host data input set-up time before write data strobe deassertion Host data input hold time after write data strobe deassertion 1. 2. 3.
1
Max
-- -- --
Unit
ns ns
1.8 + TREFCLK 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK -- 2.7 3.0 2.5 4.0 -- -- -- -- 5 + TREFCLK 5 + (1.5 x TREFCLK) 5 + (2.5 x TREFCLK) 1.8 + TREFCLK 1.7 3.2 -- -- -- 11.5 -- -- -- -- 7.5 7.5 7.2
ns ns ns ns ns ns ns ns ns ns ns ns ns
103 104 105 106 107 108 109 110 111
ns ns ns ns ns ns
112 201 202 Notes:
Attributes refers to the following signals: HCS, HA[11-29], HCID[0-4], HDST, HRW, HRDS, and HWBSn. This specification is tested in dual strobe mode. Timing in single strobe mode is guaranteed by design. All values listed in this table are tested or guaranteed by design.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-14 Freescale Semiconductor
AC Timings
Figure 2-9 shows DSI asynchronous read signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HWBSn 2
100
101
112 HDBSn1 HRDS2 102 103
107 104 HD[0-63] 106
105
109
HTA3 108 110
HTA4
111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pulldown implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-9.
Asynchronous Single and Dual Modes Read Timing Diagram
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-15
Specifications
Figure 2-10 shows DSI asynchronous write signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2
100
101
112 HDBSn1 HWBSn2 201 202 HD[0-63] 109
102
106 HTA3
108
110
HTA4
111 Notes: 1. 2. 3. 4. Used for single-strobe mode access. Used for dual-strobe mode access. HTA released at logic 0 (DCR[HTAAD] = 0) at end of access; used with pull-down implementation. HTA released at logic 1 (DCR[HTAAD] = 1) at end of access; used with pull-up implementation.
Figure 2-10.
Asynchronous Single and Dual Modes Write Timing Diagram
Figure 2-11 shows DSI asynchronous broadcast write signals timing.
HCS HA[11-29] HCID[0-4] HDST HRW1 HRDS2
100
101
112 HWBSn HDBSn1 2 102 201 202 HD[0-63]
Notes:
1. 2.
Used for single-strobe mode access. Used for dual-strobe mode access.
Figure 2-11.
Asynchronous Broadcast Write Timing Diagram
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-16 Freescale Semiconductor
AC Timings
2.5.6.2 DSI Synchronous Mode
Table 2-16.
Number
120 121 122 123 124 125 126 127 Notes: 1.
DSI Inputs--Synchronous Mode
Expression
HTC (0.5 0.1) x HTC (0.5 0.1) x HTC -- -- -- -- --
Characteristic
HCLKIN Cycle Time1 HCLKIN high pulse width HCLKIN Low pulse width HA[11-29] inputs set-up time HD[0-63] inputs set-up time HCID[0-4] inputs set-up time All other inputs set-up time All inputs hold time
Minimum
14.3 5.7 5.7 2.4 3.4 3.3 2.5 2.2
Maximum
55.6 33.3 33.3 -- -- -- -- --
Units
ns ns ns ns ns ns ns ns
Values are based on a frequency range of 18-70 MHz. See Table 2-6 for HCLKIN limits.
Table 2-17.
Number
128 129 130 131 132 133 134 135
DSI Outputs--Synchronous Mode
Minimum
2.0 -- 1.8 -- 1.5 -- 1.7 --
Characteristic
HCLKIN high to HD[0-63] output active HCLKIN high to HD[0-63] output valid HD[0-63] output hold time HCLKIN high to HD[0-63] output high impedance HCLKIN high to HTA output active HCLKIN high to HTA output valid HTA output hold time HCLKIN high to HTA high impedance
Maximum
-- 8.6 -- 9.4 -- 9.0 -- 5.2
Units
120 122
HCLKIN 123 HA[11-29] input signals 124 HD[0-63] input signals 125 HCID[0-4] input signals 126 All other input signals 129
121 127
127
127
127 131 130
HD[0-63] output signals
~~ ~~
128
133 132
135 134
Figure 2-12.
DSI Synchronous Mode Signals Timing Diagram
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-17
~ ~
HTA output signal
Specifications
2.5.7
TDM Timing
Table 2-18. TDM Timing
Expression
TC1 (0.5 0.1) x TC (0.5 0.1) x TC
Number
300 301 302 303 304 305 306 307 308 309 310 Notes: 1. 2. 3.
Characteristic
TDMxRCLK/TDMxTCLK TDMxRCLK/TDMxTCLK high pulse width TDMxRCLK/TDMxTCLK Low pulse width TDM receive all input set-up time TDM receive all input hold time TDMxTCLK high to TDMxTDAT/TDMxRCLK output active2,3 TDMxTCLK high to TDMxTDAT/TDMxRCLK output valid2,3 All output hold time2 TDMxTCLK high to TDmXTDAT/TDMxRCLK output high impedance2,3 TDMxTCLK high to TDMXTSYN output valid2 TDMxTSYN output hold time2
Minimum
20 8 8 2.5 2.5 3 -- 4 -- -- 3.9
Maximum
-- -- -- -- -- -- 12 -- 11 11 --
Units
ns ns ns ns ns ns ns ns ns ns ns
Values are based on a frequency range of 9-50 MHz. Values are based on 30 pF capacitive load. When configured as an output, TDMxRCLK acts as a second data link. See Chapter 22 of the MSC8102 Reference Manual for details.
300 301 TDMxRCLK 304 303 TDMxRDAT 304 303 TDMxRSYN 302
Figure 2-13.
TDM Inputs Signals
300 301 TDMxTCLK 306 302 308
~~ ~~
305 TDMxTDAT TDMxRCLK 309 TDMxTSYN
307
310
Figure 2-14.
TDM Output Signals
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-18 Freescale Semiconductor
AC Timings
2.5.8
No.
400 401 402
UART Timing
Table 2-19.
Characteristics
URXD and UTXD inputs high/low duration URXD and UTXD inputs rise/fall time UTXD output rise/fall time
UART Timing
Expression
16 x TREFCLK
Min
160.0
Max
-- 10 10
Unit
ns ns ns
401
401
UTXD, URXD inputs 400 400
Figure 2-15.
UART Input Timing
402
402
UTXD output
Figure 2-16.
UART Output Timing
2.5.9
No.
500 501 502 503
Timer Timing
Table 2-20.
Characteristics
TIMERx frequency TIMERx Input high period TIMERx output low period TIMERx propagations delay from its clock input
Timer Timing
Min.
10.9 4.0 4.0 3.3
Max
-- -- -- 10.0
Unit
ns ns ns ns
500 501 TIMERx (Input) 503 TIMERx (Output) 502
Figure 2-17.
Timer Timing
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-19
Specifications
2.5.10 GPIO Timing
Table 2-21.
No.
601 602 603 604 605
GPIO Timing
Min
-- 1.5 -- 4.5 0.5
Characteristics
REFCLK edge to GPIO out valid (GPIO out delay time) REFCLK edge to GPIO out not valid (GPIO out hold time) REFCLK edge to high impedance on GPIO out GPIO in valid to REFCLK edge (GPIO in set-up time) REFCLK edge to GPIO in not valid (GPIO in hold time)
Max
8.5 -- 5.4 -- --
Unit
ns ns ns ns ns
REFCLK 601 603 GPIO (Output) High Impedance 602
604 GPIO (Input)
605
Valid
Figure 2-18.
GPIO Timing
2.5.11 EE Signals
Table 2-22.
Number
65 66 Notes: 1. 2. EE0 (input) EE1 (output)
EE Pin Timing
Type
Asynchronous Synchronous to Core clock
Characteristics
Minimum
4 core clock periods 1 core clock period
The core clock is the SC140 core clock. The ratio between the core clock and CLKOUT is configured during power-on-reset. Refer to Table 1-4 on page 1-6 for detailed information about EE pin functionality.
Figure 2-19 shows the signal behavior of the EE pins.
65 EE0 in 66 EE1 out
Figure 2-19.
EE Pins Timing
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-20 Freescale Semiconductor
AC Timings
2.5.12 JTAG Signals
Table 2-23. JTAG Timing
All frequencies No. Characteristics Min
700 701 702 703 704 705 706 707 708 709 710 711 712 713 Note: TCK frequency of operation (1/(TC x 3); maximum 22 MHz) TCK cycle time TCK clock pulse width measured at VM = 1.6 V TCK rise and fall times Boundary scan input data set-up time Boundary scan input data hold time TCK low to output data valid TCK low to output high impedance TMS, TDI data set-up time TMS, TDI data hold time TCK low to TDO data valid TCK low to TDO high impedance TRST assert time TRST set-up time to TCK low 0.0 45.0 21.0 0.0 5.0 24.0 0.0 0.0 5.0 25.0 0.0 0.0 100.0 40.0
Unit Max
22.0 -- -- 3.0 -- -- 40.0 40.0 -- -- 44.0 20.0 -- -- MHz ns ns ns ns ns ns ns ns ns ns ns ns ns
All timings apply to OnCE module data transfers as the OnCE module uses the JTAG port as an interface.
701 702 TCK (Input) VIH 703 VM VIL 703 VM
Figure 2-20.
Test Clock Input Timing Diagram
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 2-21
Specifications
TCK (Input)
VIH VIL 704 705
Data Inputs 706 Data Outputs 707 Data Outputs
Input Data Valid
Output Data Valid
Figure 2-21.
Boundary Scan (JTAG) Timing Diagram
VIH
TCK (Input) TDI TMS (Input)
VIL 708 Input Data Valid 710 709
TDO (Output) 711 TDO (Output)
Output Data Valid
Figure 2-22.
TCK (Input) 713 TRST (Input) 712
Test Access Port Timing Diagram
Figure 2-23.
TRST Timing Diagram
MSC8102 Quad Core Digital Signal Processor, Rev. 12 2-22 Freescale Semiconductor
Packaging
3
This chapter provides information on the MSC8102 package, including diagrams of the package pinouts and tables showing how the signals discussed in Chapter 1 are allocated. The MSC8102 is available in a 431-pin High Temperature Coefficient for Expansion Flip Chip-Ceramic Ball Grid Array (FC-CBGA (HCTE)).
3.1 FC-CBGA (HCTE) Package Description
Figure 3-1 and Figure 3-2 show top and bottom views of the FC-CBGA (HCTE) package, including pinouts. To conform to JDEC requirements, the package is based on a 23 x 23 position (20 x 20 mm) layout with the outside perimeter depopulated. Therefore, ball position numbering starts with B2. Signal names shown in the figures are typically the signal assigned after reset. Signals that are only used during power-on reset (SWTE, DSISYNC, DSI64, MODCK[1-2], CNFGS, and CHIP_ID[0-3]) are not shown in these figures if there is another signal assigned to the pin after reset. Also, there are several signals that are designated as IRQ lines immediately after reset, but represent duplicate IRQ lines that should be reconfigured by the user. To represent these signals uniquely in the figures, the second functions (BADDR[29-31], DP[1-7], and INT_OUT) are used. Table 3-1 lists the MSC8102 signals alphabetically by signal name. Connections with multiple names are listed individually by each name. Signals with programmable polarity are shown both as signals which are asserted low (default) and high (that is, NAME/NAME). Table 3-2 lists the signals numerically by pin number. Each pin number is listed once with the various signals that are multiplexed to it. For simplicity, signals with programmable polarity are shown in this table only with their default name (asserted low).
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-1
Packaging
Top View
2
B
3
VDD
4
GND
5
GND
6
NMI_ OUT
7
GND
8
VDD
9
GND
10
VDD
11
GND
12
VDD
13
GND
14
VDD
15
GND
16
VDD
17
GND
18
VDD
19
GPIO0
20
VDD
21
VDD
22
GND
C
GND
VDD
TDO
S GPIO28 HCID1 RESET
GND
VDD
GND
VDD
GND
VDD
GND
GND
GPIO30 GPIO2
GPIO1
GPIO7
GPIO3
GPIO5
GPIO6
D
TDI
EE0
EE1
GND
VDDH
HCID2
HCID3
GND
VDD
GND
VDD
GND
VDD
VDD
GPIO31 GPIO29
VDDH
GPIO4
VDDH
GND
GPIO8
E
TCK
TRST
TMS
HRESET GPIO27 HCID0
GND
VDD
GND
VDD
GND
VDD
GND
GND
VDD
GND
GND
GPIO9 GPIO13 GPIO10 GPIO12
F
PO RESET
RST CONF
NMI
HA29
HA22
GND
VDD
VDD
VDD
GND
VDD
GND
VDD
GND
VDD
GPIO20 GPIO18 GPIO16 GPIO11 GPIO14 GPIO19
G
HA24
HA27
HA25
HA23
HA17
PWE0
VDD
VDD
BADDR 31
BM0
ABB
VDD
INT_ OUT
VDD
VDD
CS1
BCTL0 GPIO15
GND
GPIO17 GPIO22
H
HA20
HA28
VDD
HA19
TEST
PSD CAS
PGTA
VDD
BM1
ARTRY
AACK
DBB
HTA
VDD
TT4
CS4
GPIO24 GPIO21
VDD
VDDH
A31
J
HA18
HA26
VDD
HA13
GND
PSDA BADDR MUX 27
VDD
CLKIN
BM2
DBG
VDD
GND
VDD
TT3
PSDA10 BCTL1 GPIO23
GND
GPIO25
A30
K
HA15
HA21
HA16
PWE3
PWE1
POE
BADDR DLLIN 30
GND
GND
GND
GND CLKOUT
VDD
TT2
ALE
CS2
GND
A26
A29
A28
L
HA12
HA14
HA11
VDDH
VDDH
BADDR BADDR 28 29
GND
GND
GND
VDDH
GND
GND
CS3
VDDH
A27
A25
A22
SC M
M
HD28
HD31
VDDH
GND
GND
GND
VDD
VDDH
GND
GND
VDDH
HB RST
VDDH
VDDH
GND
VDDH
A24
A21
81 02
N
HD26
HD30
HD29
HD24
PWE2
VDDH
HWBS 0
HBCS
GND
GND
HRDS
BG
HCS
CS0
PSDWE GPIO26
A23
A20
P
HD20
HD27
HD25
HD23
HWBS 3 HWBS 6 HWBS 7
HWBS 2 HWBS 4 HWBS 5
HWBS HCLKIN 1
GND
GNDSYN VCCSYN
GND
GND
TA
BR
TEA
PSD VAL
DP0
VDDH
GND
A19
R
HD18
VDDH
GND
HD22
TSZ1
TSZ3
GBL
VDD
VDD
VDD
TT0
DP7
DP6
DP3
TS
DP2
A17
A18
A16
T
HD17
HD21
HD1
HD0
TSZ0
TSZ2
TBST
VDD
D16
TT1
D21
D23
DP5
DP4
DP1
D30
GND
A15
A14
U
HD16
HD19
HD2
D2
D3
D6
D8
D9
D11
D14
D15
D17
D19
D22
D25
D26
D28
D31
VDDH
A12
A13
V
HD3
VDDH
GND
D0
D1
D4
D5
D7
D10
D12
D13
D18
D20
GND
D24
D27
D29
A8
A9
A10
A11
W
HD6
HD5
HD4
GND
GND
VDDH
VDDH
GND
HDST1 HDST0
VDDH
GND
HD40
VDDH
HD33
VDDH
HD32
GND
GND
A7
A6
Y
HD7
HD15
VDDH
HD9
VDD
HD60
HD58
GND
VDDH
HD51
GND
VDDH
HD43
GND
VDDH
GND
HD37
HD34
VDDH
A4
A5
AA
VDD
HD14
HD12
HD10
HD63
HD59
GND
VDDH
HD54
HD52
VDDH
GND
VDDH
HD46
GND
HD42
HD38
HD35
A0
A2
A3
AB
GND
HD13
HD11
HD8
HD62
HD61
HD57
HD56
HD55
HD53
HD50
HD49
HD48
HD47
HD45
HD44
HD41
HD39
HD36
A1
VDD
Figure 3-1.
MSC8102 High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (High CTE FCCBGA), Top View
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-2 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Bottom View
22
B GND
21
VDD
20
VDD
19
GPIO0
18
VDD
17
GND
16
VDD
15
GND
14
VDD
13
GND
12
VDD
11
GND
10
VDD
9
GND
8
VDD
7
GND
6
NMI_ OUT
5
GND
4
GND
3
VDD
2
C
GPIO6
GPIO5
GPIO3
GPIO7
GPIO1
GPIO2 GPIO30
GND
GND
VDD
GND
VDD
GND
VDD
GND
HCID1 GPIO28
S RESET
TDO
VDD
GND
D
GPIO8
GND
VDDH
GPIO4
VDDH
GPIO29 GPIO31
VDD
VDD
GND
VDD
GND
VDD
GND
HCID3
HCID2
VDDH
GND
EE1
EE0
TDI
E
GPIO12 GPIO10 GPIO13 GPIO9
GND
GND
VDD
GND
GND
VDD
GND
VDD
GND
VDD
GND
HCID0 GPIO27 HRESET
TMS
TRST
TCK
F GPIO19 GPIO14 GPIO11 GPIO16 GPIO18 GPIO20
VDD
GND
VDD
GND
VDD
GND
VDD
VDD
VDD
GND
HA22
HA29
NMI
RST CONF
PO RESET
G GPIO22 GPIO17
GND
GPIO15 BCTL0
CS1
VDD
VDD
INT_ OUT
VDD
ABB
BM0
BADDR 31
VDD
VDD
PWE0
HA17
HA23
HA25
HA27
HA24
H
A31
VDDH
VDD
GPIO21 GPIO24
CS4
TT4
VDD
HTA
DBB
AACK
ARTRY
BM1
VDD
PGTA
PSD CAS
TEST
HA19
VDD
HA28
HA20
J
A30
GPIO25
GND
GPIO23 BCTL1 PSDA10
TT3
VDD
GND
VDD
DBG
BM2
CLKIN
VDD
BADDR PSDA 27 MUX BADDR 30
GND
HA13
VDD
HA26
HA18
K
A28
A29
A26
GND
CS2
ALE
TT2
VDD
CLKOUT GND
GND
GND
GND
DLLIN
POE
PWE1
PWE3
HA16
HA21
HA15
L
A22
A25
A27
VDDH
CS3
GND
GND
VDDH
GND
GND
GND
BADDR BADDR 29 28
VDDH
VDDH
HA11
HA14
HA12
M
A21
A24
VDDH
GND
VDDH
VDDH
M
SC
HB RST
VDDH
81
02
GND
GND
VDDH
VDD
GND
GND
GND
VDDH
HD31
HD28
N
A20
A23
GPIO26 PSDWE
CS0
HCS
BG
HRDS
GND
GND
HBCS
HWBS 0 HWBS 1
VDDH
PWE2
HD24
HD29
HD30
HD26
P
A19
GND
VDDH
DP0
PSD VAL
TEA
BR
TA
GND
GND
VCCSYN GND SYN
GND
HCLKIN
HWBS 2 HWBS 4 HWBS 5
HWBS 3 HWBS 6 HWBS 7
HD23
HD25
HD27
HD20
R
A16
A18
A17
DP2
TS
DP3
DP6
DP7
TT0
VDD
VDD
VDD
GBL
TSZ3
TSZ1
HD22
GND
VDDH
HD18
T
A14
A15
GND
D30
DP1
DP4
DP5
D23
D21
TT1
D16
VDD
TBST
TSZ2
TSZ0
HD0
HD1
HD21
HD17
U
A13
A12
VDDH
D31
D28
D26
D25
D22
D19
D17
D15
D14
D11
D9
D8
D6
D3
D2
HD2
HD19
HD16
V
A11
A10
A9
A8
D29
D27
D24
GND
D20
D18
D13
D12
D10
D7
D5
D4
D1
D0
GND
VDDH
HD3
W
A6
A7
GND
GND
HD32
VDDH
HD33
VDDH
HD40
GND
VDDH
HDST0 HDST1
GND
VDDH
VDDH
GND
GND
HD4
HD5
HD6
Y
A5
A4
VDDH
HD34
HD37
GND
VDDH
GND
HD43
VDDH
GND
HD51
VDDH
GND
HD58
HD60
VDD
HD9
VDDH
HD15
HD7
AA
A3
A2
A0
HD35
HD38
HD42
GND
HD46
VDDH
GND
VDDH
HD52
HD54
VDDH
GND
HD59
HD63
HD10
HD12
HD14
VDD
AB
VDD
A1
HD36
HD39
HD41
HD44
HD45
HD47
HD48
HD49
HD50
HD53
HD55
HD56
HD57
HD61
HD62
HD8
HD11
HD13
GND
Figure 3-2.
MSC8102 High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (High CTE FCCBGA), Bottom View
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-3
Packaging
Table 3-1.
Signal Name
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 AACK ABB ALE ARTRY
MSC8102 Signal Listing By Name
Location Designator
AA20 AB21 AA21 AA22 Y21 Y22 W22 W21 V19 V20 V21 V22 U21 U22 T22 T21 R22 R20 R21 P22 N22 M22 L22 N21 M21 L21 K20 L20 K22 K21 J22 H22 H12 G12 K17 H11
Signal Name
BADDR27 BADDR28 BADDR29 BADDR30 BADDR31 BCTL0 BCTL1 BG BNKSEL0 BNKSEL1 BNKSEL2 BM0 BM1 BM2 BR CHIP_ID0 CHIP_ID1 CHIP_ID2 CHIP_ID3 CLKIN CLKOUT CNFGS CS0 CS1 CS2 CS3 CS4 CS5 CS5 CS6 CS7 D0 D1 D2 D3 D4
Location Designator
J8 L7 L8 K8 G10 G18 J18 N16 G11 H10 J11 G11 H10 J11 P16 B19 C18 C17 D17 J10 K14 W3 N18 G17 K18 L18 H17 K16 J18 J16 H16 V5 V6 U5 U6 V7
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-4 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-1.
Signal Name
D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 D23 D24 D25 D26 D27 D28 D29 D30 D31 D32 D33 D34 D35 D36 D37 D38 D39 D40
MSC8102 Signal Listing By Name (Continued)
Location Designator
V8 U7 V9 U8 U9 V10 U10 V11 V12 U11 U12 T12 U13 V13 U14 V14 T14 U15 T15 V16 U16 U17 V17 U18 V18 T19 U19 W18 W16 Y19 AA19 AB20 Y18 AA18 AB19 W14
Signal Name
D41 D42 D43 D44 D45 D46 D47 D48 D49 D50 D51 D52 D53 D54 D55 D56 D57 D58 D59 D60 D61 D62 D63 DACK1 DACK1 DACK2 DACK2 DACK3 DACK4 DBB DBG DLLIN DONE1 DONE2 DP0 DP1
Location Designator
AB18 AA17 Y14 AB17 AB16 AA15 AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10 AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 G21 T18 F22 R19 T17 T16 H13 J12 K9 F19 G22 P19 T18
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-5
Packaging
Table 3-1.
Signal Name
DP2 DP3 DP4 DP5 DP6 DP7 DRACK1 DRACK2 DREQ1 DREQ1 DREQ2 DREQ2 DREQ3 DREQ4 DSI64 DSISYNC EE0 EE1 EXT_BG2 EXT_BG3 EXT_BR2 EXT_BR3 EXT_DBG2 EXT_DBG3 GBL GND GND GND GND GND GND GND GND GND GND GND
MSC8102 Signal Listing By Name (Continued)
Location Designator
R19 R17 T17 T16 R16 R15 F19 G22 G19 P19 F18 R17 R16 R15 U4 T4 D3 D4 T18 T16 P19 R17 R19 T17 R10 B4 B5 B7 B9 B11 B13 B15 B17 B22 C2 C8
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND
Location Designator
C10 C12 C14 C15 D5 D9 D11 D13 D21 E8 E10 E12 E14 E15 E17 E18 F7 F11 F13 F15 G20 J6 J14 J20 K10 K11 K12 K13 K19 L9 L10 L14 L16 L17 M5 M6
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-6 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-1.
Signal Name
GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GNDSYN GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6
MSC8102 Signal Listing By Name (Continued)
Location Designator
M7 M10 M14 M19 N10 N14 P10 P13 P14 P21 R4 T20 V4 V15 W5 W6 W9 W13 W19 W20 Y9 Y12 Y15 Y17 AA8 AA13 AA16 AB2 P11 B19 C18 C17 C20 D19 C21 C22
Signal Name
GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO21 GPIO22 GPIO23 GPIO24 GPIO25 GPIO26 GPIO27 GPIO28 GPIO29 GPIO30 GPIO31 HA11 HA12 HA13 HA14 HA15 HA16 HA17 HA18 HA19 HA20 HA21
Location Designator
C19 D22 E19 E21 F20 E22 E20 F21 G19 F19 G21 F18 F22 F17 H19 G22 J19 H18 J21 N20 E6 C6 D17 C16 D16 L4 L2 J5 L3 K2 K4 G6 J2 H5 H2 K3
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-7
Packaging
Table 3-1.
Signal Name
HA22 HA23 HA24 HA25 HA26 HA27 HA28 HA29 HBCS HBRST HCID0 HCID1 HCID2 HCID3 HCLKIN HCS HD0 HD1 HD2 HD3 HD4 HD5 HD6 HD7 HD8 HD9 HD10 HD11 HD12 HD13 HD14 HD15 HD16 HD17 HD18 HD19
MSC8102 Signal Listing By Name (Continued)
Location Designator
F6 G5 G2 G4 J3 G3 H3 F5 N9 M16 E7 C7 D7 D8 P9 N17 T5 T4 U4 V2 W4 W3 W2 Y2 AB5 Y5 AA5 AB4 AA4 AB3 AA3 Y3 U2 T2 R2 U3
Signal Name
HD20 HD21 HD22 HD23 HD24 HD25 HD26 HD27 HD28 HD29 HD30 HD31 HD32 HD33 HD34 HD35 HD36 HD37 HD38 HD39 HD40 HD41 HD42 HD43 HD44 HD45 HD46 HD47 HD48 HD49 HD50 HD51 HD52 HD53 HD54 HD55
Location Designator
P2 T3 R5 P5 N5 P4 N2 P3 M2 N4 N3 M3 W18 W16 Y19 AA19 AB20 Y18 AA18 AB19 W14 AB18 AA17 Y14 AB17 AB16 AA15 AB15 AB14 AB13 AB12 Y11 AA11 AB11 AA10 AB10
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-8 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-1.
Signal Name
HD56 HD57 HD58 HD59 HD60 HD61 HD62 HD63 HDBE4 HDBE5 HDBE6 HDBE7 HDBS4 HDBS5 HDBS6 HDBS7 HDST0 HDST1 HRDE HRDS HRESET HRW HTA HWBS0 HWBS1 HWBS2 HWBS3 HWBS4 HWBS5 HWBS6 HWBS7 INT_OUT IRQ1 IRQ1 IRQ1 IRQ2
MSC8102 Signal Listing By Name (Continued)
Location Designator
AB9 AB8 Y8 AA7 Y7 AB7 AB6 AA6 R7 T7 R6 T6 R7 T7 R6 T6 W11 W10 N15 N15 E5 N15 H14 N8 P8 P7 P6 R7 T7 R6 T6 G14 C20 R10 T18 D19
Signal Name
IRQ2 IRQ2 IRQ3 IRQ3 IRQ3 IRQ4 IRQ4 IRQ4 IRQ5 IRQ5 IRQ5 IRQ5 IRQ6 IRQ6 IRQ7 IRQ7 IRQ7 IRQ8 IRQ9 IRQ10 IRQ11 IRQ12 IRQ13 IRQ14 IRQ15 MODCK1 MODCK2 NMI NMI_OUT PBPL3 PBS0 PBS1 PBS2 PBS3 PBS4 PBS5
Location Designator
K8 R19 C21 G10 R17 C22 G12 T17 C19 H13 L8 T16 D22 R16 E19 G14 R15 E21 F20 E22 E20 F21 J19 H18 J21 V2 W4 F4 B6 H7 G7 K6 N6 K5 R7 T7
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-9
Packaging
Table 3-1.
Signal Name
PBS6 PBS7 PGPL0 PGPL1 PGPL2 PGPL4 PGPL5 PGTA POE PORESET PPBS PSDA10 PSDAMUX PSDCAS PSDDQM0 PSDDQM1 PSDDQM2 PSDDQM3 PSDDQM4 PSDDQM5 PSDDQM6 PSDDQM7 PSDRAS PSDVAL PSDWE PWE0 PWE1 PWE2 PWE3 PWE4 PWE5 PWE6 PWE7 PUPMWAIT RSTCONF SRESET
MSC8102 Signal Listing By Name (Continued)
Location Designator
R6 T6 J17 N19 K7 H8 J7 H8 K7 F2 H8 J17 J7 H7 G7 K6 N6 K5 R7 T7 R6 T6 K7 P18 N19 G7 K6 N6 K5 R7 T7 R6 T6 H8 F3 C5
Signal Name
SWTE TA TBST TC0 TC1 TC2 TCK TDI TDM0RCLK TDM0RDAT TDM0RSYN TDM0TCLK TDM0TDAT TDM0TSYN TDM1RCLK TDM1RDAT TDM1RSYN TDM1TCLK TDM1TDAT TDM1TSYN TDM2RCLK TDM2RDAT TDM2RSYN TDM2TCLK TDM2TDAT TDM2TSYN TDM3RCLK TDM3RDAT TDM3RSYN TDM3TCLK TDM3TDAT TDM3TSYN TDO TEA TEST TIMER0
Location Designator
T5 P15 T10 G11 H10 J11 E2 D2 J21 N20 H18 G22 J19 H19 F22 F17 F18 F19 G21 G19 E20 F21 E22 E21 F20 E19 C19 D22 C22 D19 C21 C20 C4 P17 H6 C18
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-10 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-1.
Signal Name
TIMER1 TIMER2 TIMER3 TMCLK TMS TRST TS TSZ0 TSZ1 TSZ2 TSZ3 TT0 TT1 TT2 TT3 TT4 URXD UTXD VCCSYN VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD
MSC8102 Signal Listing By Name (Continued)
Location Designator
C17 C16 D16 C16 E4 E3 R18 T8 R8 T9 R9 R14 T13 K16 J16 H16 E6 C6 P12 B8 B10 B12 B14 B16 B18 B20 B21 C3 C9 C11 C13 D10 D12 D14 D15 E9
Signal Name
VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDDH VDDH VDDH VDDH
Location Designator
E11 E13 E16 F8 F9 F10 F12 F14 F16 G8 G9 G13 G15 G16 H4 H9 H15 H20 J4 J9 J13 J15 K15 M8 R11 R12 R13 T11 Y6 AA2 B3 AB22 D6 D18 D20 H21
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-11
Packaging
Table 3-1.
Signal Name
VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
MSC8102 Signal Listing By Name (Continued)
Location Designator
L5 L6 L15 L19 M4 M9 M15 M17 M18 M20 N7 P20 R3 U20
Signal Name
VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH VDDH
Location Designator
V3 W7 W8 W12 W15 W17 Y4 Y10 Y13 Y16 Y20 AA9 AA12 AA14
Note: This table lists every signal name. Because many signals are multiplexed, an individual ball designator number may be listed several times.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-12 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-2.
Locator Designator
B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19
MSC8102 Signal Listing by Ball Designator
Locator Designator
C20 C21 C22 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 D21 D22 E2 E3 E4 E5 E6 E7 E8 E9 E10 E11 E12 E13 E14 E15
Signal Name
VDD GND GND NMI_OUT GND VDD GND VDD GND VDD GND VDD GND VDD GND VDD GPIO0/CHIP_ID0 VDD VDD GND GND VDD TDO SRESET GPIO28/DREQ2/UTXD HCID1 GND VDD GND VDD GND VDD GND GND GPIO30/TIMER2/TMCLK GPIO2/TIMER1/CHIP_ID2 GPIO1/TIMER0/CHIP_ID1 GPIO7/TDM3RCLK/IRQ5
Signal Name
GPIO3/TDM3TSYN/IRQ1 GPIO5/TDM3TDAT/IRQ3 GPIO6/TDM3RSYN/IRQ4 TDI EE0 EE1 GND VDDH HCID2 HCID3 GND VDD GND VDD GND VDD VDD GPIO31/TIMER3 GPIO29/CHIP_ID3 VDDH GPIO4/TDM3TCLK/IRQ2 VDDH GND GPIO8/TDM3RDAT/IRQ6 TCK TRST TMS HRESET GPIO27/DREQ1/URXD HCID0 GND VDD GND VDD GND VDD GND GND
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-13
Packaging
Table 3-2.
Locator Designator
E16 E17 E18 E19 E20 E21 E22 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 F13 F14 F15 F16 F17 F18 F19 F20 F21 F22 G2 G3 G4 G5 G6 G7 G8 G9 G10 G11
MSC8102 Signal Listing by Ball Designator (Continued)
Locator Designator
G12 G13 G14 G15 G16 G17 G18 G19 G20 G21 G22 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 H14 H15 H16 H17 H18 H19 H20 H21 H22 J2 J3 J4 J5 J6 J7
Signal Name
VDD GND GND GPIO9/TDM2TSYN/IRQ7 GPIO13/TDM2RCLK/IRQ11 GPIO10/TDM2TCLK/IRQ8 GPIO12/TDM2RSYN/IRQ10 PORESET RSTCONF NMI HA29 HA22 GND VDD VDD VDD GND VDD GND VDD GND VDD GPIO20/TDM1RDAT GPIO18/TDM1RSYN/DREQ2 GPIO16/TDM1TCLK/DONE1/DRACK1 GPIO11/TDM2TDAT/IRQ9 GPIO14/TDM2RDAT/IRQ12 GPIO19/TDM1RCLK/DACK2 HA24 HA27 HA25 HA23 HA17 PWE0/PSDDQM0/PBS0 VDD VDD IRQ3/BADDR31 BM0/TC0/BNKSEL0
Signal Name
ABB/IRQ4 VDD IRQ7/INT_OUT VDD VDD CS1 BCTL0 GPIO15/TDM1TSYN/DREQ1 GND GPIO17/TDM1TDAT/DACK1 GPIO22/TDM0TCLK/DONE2/DRACK2 HA20 HA28 VDD HA19 TEST PSDCAS/PBPL3 PGTA/PUPMWAIT/PGPL4/PPBS VDD BM1/TC1/BNKSEL1 ARTRY AACK DBB/IRQ5 HTA VDD TT4/CS7 CS4 GPIO24/TDM0RSYN/IRQ14 GPIO21/TDM0TSYN VDD VDDH A31 HA18 HA26 VDD HA13 GND PSDAMUX/PGPL5
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-14 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-2.
Locator Designator
J8 J9 J10 J11 J12 J13 J14 J15 J16 J17 J18 J19 J20 J21 J22 K2 K3 K4 K5 K6 K7 K8 K9 K10 K11 K12 K13 K14 K15 K16 K17 K18 K19 K20 K21 K22 L2 L3
MSC8102 Signal Listing by Ball Designator (Continued)
Locator Designator
L4 L5 L6 L7 L8 L9 L10 L14 L15 L16 L17 L18 L19 L20 L21 L22 M2 M3 M4 M5 M6 M7 M8 M9 M10 M14 M15 M16 M17 M18 M19 M20 M21 M22 N2 N3 N4 N5
Signal Name
BADDR27 VDD CLKIN BM2/TC2/BNKSEL2 DBG VDD GND VDD TT3/CS6 PSDA10/PGPL0 BCTL1/CS5 GPIO23/TDM0TDAT/IRQ13 GND GPIO25/TDM0RCLK/IRQ15 A30 HA15 HA21 HA16 PWE3/PSDDQM3/PBS3 PWE1/PSDDQM1/PBS1 POE/PSDRAS/PGPL2 IRQ2/BADDR30 DLLIN GND GND GND GND CLKOUT VDD TT2/CS5 ALE CS2 GND A26 A29 A28 HA12 HA14
Signal Name
HA11 VDDH VDDH BADDR28 IRQ5/BADDR29 GND GND GND VDDH GND GND CS3 VDDH A27 A25 A22 HD28 HD31 VDDH GND GND GND VDD VDDH GND GND VDDH HBRST VDDH VDDH GND VDDH A24 A21 HD26 HD30 HD29 HD24
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-15
Packaging
Table 3-2.
Locator Designator
N6 N7 N8 N9 N10 N14 N15 N16 N17 N18 N19 N20 N21 N22 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13 P14 P15 P16 P17 P18 P19 P20 P21 P22
MSC8102 Signal Listing by Ball Designator (Continued)
Locator Designator
R2 R3 R4 R5 R6 R7 R8 R9 R10 R11 R12 R13 R14 R15 R16 R17 R18 R19 R20 R21 R22 T2 T3 T4 T5 T6 T7 T8 T9 T10 T11 T12 T13 T14 T15
Signal Name
PWE2/PSDDQM2/PBS2 VDDH HWBS0 HBCS GND GND HRDS/HRW/HRDE BG HCS CS0 PSDWE/PGPL1 GPIO26/TDM0RDAT A23 A20 HD20 HD27 HD25 HD23 HWBS3 HWBS2 HWBS1 HCLKIN GND GNDSYN VCCSYN GND GND TA BR TEA PSDVAL DP0/DREQ1/EXT_BR2 VDDH GND A19
Signal Name
HD18 VDDH GND HD22 HWBS6/HDBS6/HWBE6/HDBE6/PWE6/ PSDDQM6/PBS6 HWBS4/HDBS4/HWBE4/HDBE4/PWE4/ PSDDQM4/PBS4 TSZ1 TSZ3 IRQ1/GBL VDD VDD VDD TT0 IRQ7/DP7/DREQ4 IRQ6/DP6/DREQ3 IRQ3/DP3/DREQ2/EXT_BR3 TS IRQ2/DP2/DACK2/EXT_DBG2 A17 A18 A16 HD17 HD21 HD1/DSISYNC HD0/SWTE HWBS7/HDBS7/HWBE7/HDBE7/PWE7/ PSDDQM7/PBS7 HWBS5/HDBS5/HWBE5/HDBE5/PWE5/ PSDDQM5/PBS5 TSZ0 TSZ2 TBST VDD D16 TT1 D21 D23
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-16 Freescale Semiconductor
FC-CBGA (HCTE) Package Description
Table 3-2.
Locator Designator
T16 T17 T18 T19 T20 T21 T22 U2 U3 U4 U5 U6 U7 U8 U9 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 U21 U22 V2 V3 V4 V5 V6 V7 V8 V9 V10 V11
MSC8102 Signal Listing by Ball Designator (Continued)
Locator Designator
V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 W2 W3 W4 W5 W6 W7 W8 W9 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 W21 W22 Y2 Y3 Y4 Y5 Y6 Y7
Signal Name
IRQ5/DP5/DACK4/EXT_BG3 IRQ4/DP4/DACK3/EXT_DBG3 IRQ1/DP1/DACK1/EXT_BG2 D30 GND A15 A14 HD16 HD19 HD2/DSI64 D2 D3 D6 D8 D9 D11 D14 D15 D17 D19 D22 D25 D26 D28 D31 VDDH A12 A13 HD3/MODCK1 VDDH GND D0 D1 D4 D5 D7 D10 D12
Signal Name
D13 D18 D20 GND D24 D27 D29 A8 A9 A10 A11 HD6 HD5/CNFGS HD4/MODCK2 GND GND VDDH VDDH GND HDST1 HDST0 VDDH GND HD40/D40 VDDH HD33/D33 VDDH HD32/D32 GND GND A7 A6 HD7 HD15 VDDH HD9 VDD HD60/D60
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-17
Packaging
Table 3-2.
Locator Designator
Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Y21 Y22 AA2 AA3 AA4 AA5 AA6 AA7 AA8 AA9 AA10 AA11 AA12 AA13 AA14 AA15
MSC8102 Signal Listing by Ball Designator (Continued)
Locator Designator
AA16 AA17 AA18 AA19 AA20 AA21 AA22 AB2 AB3 AB4 AB5 AB6 AB7 AB8 AB9 AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
Signal Name
HD58/D58 GND VDDH HD51/D51 GND VDDH HD43/D43 GND VDDH GND HD37/D37 HD34/D34 VDDH A4 A5 VDD HD14 HD12 HD10 HD63/D63 HD59/D59 GND VDDH HD54/D54 HD52/D52 VDDH GND VDDH HD46/D46
Signal Name
GND HD42/D42 HD38/D38 HD35/D35 A0 A2 A3 GND HD13 HD11 HD8 HD62/D62 HD61/D61 HD57/D57 HD56/D56 HD55/D55 HD53/D53 HD50/D50 HD49/D49 HD48/D48 HD47/D47 HD45/D45 HD44/D44 HD41/D41 HD39/D39 HD36/D36 A1 VDD
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-18 Freescale Semiconductor
FC-CBGA (HCTE) Package Mechanical Drawing
3.2 FC-CBGA (HCTE) Package Mechanical Drawing
Notes: 1. All dimensions in millimeters. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. 3. Maximum solder ball diameter measured parallel to Datum A. 4. Datum A, the seating plane, is determined by the spherical crowns of the solder balls.
CASE 1453-02
Figure 3-3.
MSC8102 Mechanical Information, 431-pin FC-CBGA (HCTE) Package
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 3-19
Packaging
MSC8102 Quad Core Digital Signal Processor, Rev. 12 3-20 Freescale Semiconductor
Design Considerations
This chapter includes design and layout guidelines for manufacturing boards using the MSC8102.
4
4.1 Power Supply Design and Layout Considerations
The input voltage must not exceed the I/O supply VDDH by more than 2.5 V at any time, including during power-on reset. In turn VDDH must not exceed VDD/VCCSYN by more than 2.6 V at any time, including during power-on reset. VDD/VCCSYN must not exceed VDDH by more than 0.4 V at any time, including during power-on reset. Use the following guidelines for power-up and power-down sequences: * Assert PORESET before applying power and keep the signal driven low until the power reaches the required minimum power levels. This can be implemented via a weak pull-down resistor. * CLKIN can be held low or allowed to toggle during the beginning of the power-up sequence. However, CLKIN must start toggling before the deassertion of PORESET and after both power supplies have reached nominal voltage levels. * To maintain the proper relationship and power-up sequence between the power levels, the recommendation is to use "bootstrap" diodes between the power rails, as shown in Figure 4-1.
I/O Power MUR420 MUR420 MUR420 Core/PLL Supply MUR420
3.3 V (VDDH )
1.6 V (VDD/VCCSYN )
Figure 4-1.
Bootstrap Diodes for Power-Up Sequencing
Select the bootstrap diodes such that a nominal VDD/VCCSYN is sourced from the VDDH power supply until the VDD/VCCSYN power supply becomes active. In Figure 4-1, four MUR420 Schottky barrier diodes are connected in series; each has a forward voltage (VF) of 0.6 V at high currents, so these diodes provide a 2.4 V drop, maintaining 0.9 V on the 1.6 V power line. Once the core/PLL power supply stabilizes at 1.6 V, the bootstrap diodes will be reverse biased with negligible leakage current. The VF should be effective at the current levels required by the processor. Do not use diodes with a nominal VF that drops too low at high current. Figure 4-2 shows the recommended power decoupling circuit for the core power supply. The voltage regulator and the decoupling capacitors should supply the required device current without any drop in voltage on the device pins. The voltage on the package pins should not drop below 1.5 V even for a very short spikes. This can be achieved by using the following guidelines:
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-1
Design Considerations
-- For the core supply, use a voltage regulator rated at 1.6 V with nominal rating of at least 3 A. This rating does not reflect actual average current draw, but is recommended because it resists changes imposed by transient spikes and has better voltage recovery time than lower current rated supplies. -- Decouple the supply using low-ESR capacitors mounted as close as possible to the socket. Figure 4-2 shows three capacitors in parallel to reduce the resistance. Three capacitors is a recommended minimum number. If possible, mount at least one of the capacitors directly below the MSC8102 device.
maximum IR drop of 15 mV at 1 A 1.6 V
Power supply or Voltage Regulator
Lmax = 2 cm
One 0.01 F capacitor for every 3 Core supply pads.
MSC8102
(Imin = 3 A)
+ -
Bulk/Tantalum capacitors with low ESR and ESL Note: Use at least three capacitors. Each capacitor must be at least 150 F.
High Freq. capacitors (very low ESR and ESL)
Figure 4-2.
Core Power Supply Decoupling
Each VCC and VDD pin on the MSC8102 should be provided with a low-impedance path to the board power supply. Similarly, each GND pin should be provided with a low-impedance path to ground. The power supply pins drive distinct groups of logic on the chip. The VCC power supply should be bypassed to ground using at least four 0.1 F by-pass capacitors located as closely as possible to the four sides of the package. The capacitor leads and associated printed circuit traces connecting to chip VCC, VDD, and GND should be kept to less than half an inch per capacitor lead. A four-layer board is recommended, employing two inner layers as VCC and GND planes. All output pins on the MSC8102 have fast rise and fall times. PCB trace interconnection length should be minimized in order to minimize undershoot and reflections caused by these fast output switching times. This recommendation particularly applies to the address and data busses. Maximum PCB trace lengths of six inches are recommended. For the DSI control signals in Synchronous mode, make sure that the layout supports the DSI AC timing requirements and minimizes any signal crosstalk. Capacitance calculations should consider all device loads as well as parasitic capacitances due to the PCB traces. Attention to proper PCB layout and bypassing becomes especially critical in systems with higher capacitive loads because these loads create higher transient currents in the VCC, VDD, and GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care should be taken to minimize the noise levels on the PLL supply pins. There is one pair of PLL supply pins: VCCSYN-GNDSYN. To ensure internal clock stability, filter the power to the VCCSYN input with a circuit similar to the one in Figure 4-3. To filter as much noise as possible, place the circuit as close as possible to VCCSYN. The 0.01F capacitor should be closest to VCCSYN, followed by the 10-F capacitor, the 10-nH inductor, and finally the 10- resistor to VDD. These traces should be kept short and direct. Provide an extremely low impedance path to ground
MSC8102 Quad Core Digital Signal Processor, Rev. 12 4-2 Freescale Semiconductor
Connectivity Guidelines
for GNDSYN. Bypass GNDSYN to VCCSYN with a 0.01-F capacitor as close as possible to the chip package. For best results, place this capacitor on the backside of the PCB aligned with the depopulated void on the MSC8102 located in the square defined by positions, L11, L12, L13, M11, M12, M13, N11, N12, and N13.
VDD 10 10nH 10 F 0.01 F VCCSYN
Figure 4-3.
VCCSYN Bypass
Note: See the MSC8102 Design Checklist (AN2506) for additional information.
4.2 Connectivity Guidelines
Unused output pins can be disconnected, and unused input pins should be connected to their non-active value, except for the following: * If the DSI is unused (bit DDR[DSIDIS] is set), then HCS and HBCS must be tied to VDD and all the rest of the DSI signals can be disconnected. * When the DSI uses Synchronous mode, HTA must be pulled up. In asynchronous mode, HTA should be pulled either up or down depending on design requirements. * HDST can be disconnected if the DSI is in Big-endian mode, or if the DSI is in Little-endian mode and DCR[DSRFA] bit is set. * When the DSI is in 64-bit data bus mode and DCR[BEM] is cleared, HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/HDBE[1-3] and HWBS[4-7]/HDBS[4-7]/HWBE[4-7]/HDBE[4-7]/PWE[4-7]/PSDDQM[4-7]/PBS[4-7] must be tied to VDD. * When the DSI is in 32-bit data bus mode and DCR[BEM] is cleared, HWBS[1-3]/HDBS[1-3]/HWBE[1-3]/HDBE[1-3] must be tied to VDD. * When the DSI is in Asynchronous mode, HBRST and HCLKIN should either be disconnected or tied to VDD. * When using the DSI in Synchronous mode, use special care when laying out the control signals. Test the layout to make sure that it supports the specified DSI AC timing values and minimizes signal cross-coupling. * The following signals can be disconnected in single-master mode (BCR[EBM] is reset): BG, DBG, EXT_BG[2-3], EXT_DBG[2-3], GBL and TS. * The following signals must be pulled up: HRESET, SRESET, ARTRY, TA, TEA, PSDVAL, and AACK. * In single-master mode, ABB and DBB can be selected as IRQ inputs and be connected to the non-active value. In other modes, they must be pulled up.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-3
Design Considerations
* In single-master mode with the DLL disabled (that is, the DLLDIS bit in the Hard Reset Configuration Word is set), the following connections should be used: -- Connect the oscillator output through a buffer to CLKIN. -- Connect DLLIN to GND (pull low). -- Connect CLKOUT through a zero-delay buffer to the slave device (for example, SDRAM) using the following guidelines:

The maximum delay between the slave and CLKOUT must not exceed 0.7 ns. The maximum load on CLKOUT must not exceed 10 pF. Use a zero-delay buffer with a jitter less than 0.3 ns.
* If the 60x-compatible system bus is not used and SIUMCR[PBSE] is set, you can disconnect PPBS. Otherwise, pull the signal up. * The following signals: SWTE, DSISYNC, DSI64, MODCK[1-2], CNFGS, CHIPID[0-3], RSTCONF and BM[0-2] are used to configure the MSC8102 and are sampled on the deassertion of the PORESET signal. Therefore, they should be tied to GND or VDD either directly or through a pull-down or a pull-up resistor until the deassertion of the PORESET signal. * You must pull up BR, BG, DBG, EXT_BR[2-3], EXT_BG[2-3], EXT_DBG[2-3], and TS if the BCR[EBM] bit is set. * When they are used, you must pull up INT_OUT (if SIUMCR[INTODC] is cleared), NMI_OUT, and IRQxx (if not full drive). Note: For details on configuration, see the MSC8102 User's Guide and MSC8102 Reference Manual.
4.3 Recommended Clock Connections for Single-Master Mode with DLL Off
Use the guidelines shown in Figure 4-4 to connect CLKOUT to a slave device, such as an SDRAM. The zero-delay buffer can use internal or external feedback.
Buffer MSC8102
CLKIN DLLIN CLKOUT DLLDIS = 1
Zero-Delay Buffer SDRAM
Oscillator
Figure 4-4.
Example Clock Distribution In Single-Master Mode with DLL Disabled
Because the connection uses open loop timing between the internal and external clock (CLKOUT), the design must adhere to the following requirements: * The maximum delay between the CLKOUT pin to the SDRAM must be less than 0.7 ns. * The maximum external load on CLKOUT must not exceed 10 pF. * The zero-delay buffer must have a jitter of less than 0.3 ns.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 4-4 Freescale Semiconductor
Power Considerations
4.4 Power Considerations
The internal power dissipation consists of three components: PINT = PTCORE + PSIU + PBUSES + PPERIPH The power dissipation depends on the operating frequency of the different portions of the chip. To determine the power dissipation at a given frequency, the following equations should be applied: PCORE (fc) = ((PCORE - PLCO)/275) x fc + PLCO PTCORE (fc) = (PCORE x 4) PSIU (fc) = ((PSIU - PLSI)/91.67) x fc + PLSI PPERIPH (fc) = ((PPERIPH - PLPE)/91.67) x fc + PLPE PBUSES (fc) = PBUSES /91.67 x fc Where, fc is the operating frequency in MHz and all power numbers are in mW PLCO is the SC140 Core leakage power PLSI is the SIU leakage power PLPE is the peripheral leakage power To determine a total power dissipation in a specific application, the following equation should be applied for each I/O output pin:
P = C x VDDH2 x fs x 10-3
Equation 1
Where: P = power in mW C = load capacitance in pF fs = output switching frequency in MHz.
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor 4-5
Design Considerations
4.5 Thermal Design Considerations
An estimation of the chip-junction temperature, TJ, in C can be obtained from the following:
TJ = TA + (R JA x PD) Equation 2
where TA = ambient temperature near the package ( C) R JA = junction-to-ambient thermal resistance ( C/W) PD = PINT + PI/O = power dissipation in the package (W) PINT = IDD x V DD = internal power dissipation (W) PI/O = power dissipated from device on output pins (W) The power dissipation values for the MSC8102 are listed in Table 2-3. The ambient temperature for the device is the air temperature in the immediate vicinity that would cool the device. The junction-to-ambient thermal resistances are JEDEC standard values that provide a quick and easy estimation of thermal performance. There are two values in common usage: the value determined on a single layer board and the value obtained on a board with two planes. The value that more closely approximates a specific application depends on the power dissipated by other components on the printed circuit board (PCB). The value obtained using a single layer board is appropriate for tightly packed PCB configurations. The value obtained using a board with internal planes is more appropriate for boards with low power dissipation (less than 0.02 W/cm2 with natural convection) and well separated components. Based on an estimation of junction temperature using this technique, determine whether a more detailed thermal analysis is required. Standard thermal management techniques can be used to maintain the device thermal junction temperature below its maximum. If TJ appears to be too high, either lower the ambient temperature or the power dissipation of the chip. You can verify the junction temperature by measuring the case temperature using a small diameter thermocouple (40 gauge is recommended) or an infrared temperature sensor on a spot on the device case that is painted black. The MSC8102 device case surface is too shiny (low emissivity) to yield an accurate infrared temperature measurement. Use the following equation to determine TJ:
TJ = TT + ( JA x PD) Equation 3
where TT = thermocouple (or infrared) temperature on top of the package ( C) JA = thermal characterization parameter ( C/W) PD = power dissipation in the package (W) Note: See MSC8102, MSC8122, and MSC8126 Thermal Management Design Guidelines (AN2601).
MSC8102 Quad Core Digital Signal Processor, Rev. 12 4-6 Freescale Semiconductor
MSC8102 Quad Core Digital Signal Processor, Rev. 12 Freescale Semiconductor -1
Ordering Information
Consult a Freescale Semiconductor sales office or authorized distributor to determine product availability and place an order.
Core Frequency (MHz)
250 275
Part
Supply Voltage
1.6 V core 3.3 V I/O
Package Type
Pin Count
Order Number
MSC8102
High Temperature Coefficient for Expansion Flip Chip Ceramic Ball Grid Array (FC-CBGA (HCTE))
431
MSC8102M4000 MSC8102M4400
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MSC8102 Rev. 12 4/2005
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